在VHDL中,如何检查case语句的值是否部分满足某些信号值,而其余的无所谓?

时间:2019-10-12 22:23:11

标签: vhdl

case (my_state_val & val_q) is
    when ("000" & "00") => do something;
    when ("001" & "00") => do something else;
    when ("010" & "10") => do a 3rd thing;
    when ("100" & "DONT CARE") => do a non-default thing because my_state_val is valid;
    when others => default state or null;
end case;

如果这是一个if支票,我可以这样做:val_q /= "11",因为我知道我的计数器永远不会达到最高值。如何在案件陈述中这样做?

之所以要提交案例说明,是因为我不希望有30多个深度分支。

if 1 then
elsif 2 then
...
elsif 25 then
elsif 26 then
elsif 27 then
else
end if;

2 个答案:

答案 0 :(得分:1)

我建议这样做:

case (my_state_val & val_q) is when ("000" & "00") => do something; when ("001" & "00") => do something else; when ("010" & "10") => do a 3rd thing; when others => if my_state_val == "100" then do a non-default thing because my_state_val is valid else default state or null; end if; end case;

或者这个:

case (my_state_val) is when ("000") => Evaluate val_q; when ("001") => Evaluate val_q; when ("010") => Evaluate val_q; when ("100") => Evaluate val_q; when others => default state or null; end case;

答案 1 :(得分:0)

我最初尝试这样做:

case (my_state_val & val_q) is
    when ... => ....;
    ...
    when ("100" & "--") => do something;
    when others => null;
end case;

模拟成功。但是,我的导师习惯于非2008 VHDL,即使它是可综合的,也可能引起其他工程师的质疑。因此,我希望通过我们的编码准则。

我在此case语句周围使用了if-else。

 if my_state_val = "100" then
     my do something here;
 else
     case (my_state_val & val_q) is
        when ... => ....;
        ...
        -- removed "--"
        when others => null;
    end case;
end if;