我的代码VHDL可以编译，但是在wave模拟中没有得到预期的结果

Question

这可以用while，if等语句完成。但是必须用状态表的方程来完成。

LIBRARY ieee;
USE ieee.std_logic_1164.all;


entity P_4 is
           port (CK: IN std_logic;  
           S1,S0: out std_logic);
end P_4;

architecture ASINC of P_4 is  

signal y0:std_logic;
signal y2:std_logic;
signal y1:std_logic;

begin
    y0<=(not(ck) and y0) or (ck and y2 and y1) or (ck and not(y2) and not(y1));
    y1<=(ck and y1) or (y1 and not(y0)) or (not(ck) and not(y2) and y0) or (not(y2) and y1 and y0) or (not(ck) and not(y2)and y1);
    y2<=(ck and y2) or (y2 and y0) or (not(ck) and y1 and y0);
    s0<=(not(ck) and y0) or (ck and y2 and not(y1)) or (ck and not (y2) and y1);
    s1<= (ck and y2) or (y2 and y0) or ((not(ck) and y1 and not(y0)));

END ASINC;

尝试：

我尝试了此操作，但没有得到结果，输出图像与上面的图像相同。该代码编译没有错误。

LIBRARY ieee;
USE ieee.std_logic_1164.all;


entity P_4 is
           port (
              CK: IN std_logic:='0';  
           S1,S0: out std_logic
              );
end P_4;

architecture ASINC of P_4 is  

    signal y0:std_logic:='0';
    signal y2:std_logic:='0';
    signal y1:std_logic:='0';
    signal k0:std_logic;
    signal k2:std_logic;
    signal k1:std_logic;

begin
    k0<=(not(ck) and y0) or (ck and y2 and y1) or (ck and not(y2) and not(y1));
    k1<=(ck and y1) or (y1 and not(y0)) or (not(ck) and not(y2) and y0) or (not(y2) and y1 and y0) or (not(ck) and not(y2)and y1);
    k2<=(ck and y2) or (y2 and y0) or (not(ck) and y1 and y0);
    y0<=k0;
    y1<=k1;
    y2<=k2;
    s0<=(not(ck) and y0) or (ck and y2 and not(y1)) or (ck and not (y2) and y1);
    s1<= (ck and y2) or (y2 and y0) or ((not(ck) and y1 and not(y0)));

END ASINC;

Answer 1

y0 / 1/2都初始化为'U'（未初始化），因为您没有提供初始值。因此，您的布尔表达式将全部输出“ U”。在您的模拟器中，这看起来像是X（未知）。

Answer 2

仅初始化y0 / 1/2是不够的。如果使用的是TB，请确保连接到CK的信号已初始化。否则，

entity P_4 is
  port (
    CK: IN std_logic:='0';  
    S1,S0: out std_logic
);
end P_4;

请注意，您需要同时初始化y0 / 1/2和CK。