我正在尝试用VHDL制作电梯,在FPGA上实现。 它有0-12层,它有向上/向下的按钮,取决于你想去的方向和里面的按钮。我首先检查外部按钮是否工作,内部的实现是否相同。现在它编译,但模拟波形崩溃。
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity lift is
port (
CLK: in bit; --clock initialized by the waveform, for now
iUP: in std_logic_vector (3 downto 0); --input from FPGA
iDOWN: in std_logic_vector (3 downto 0); --output
iBUTTON: in std_logic_vector (3 downto 0); --input from inside the elevator
W: in BIT; --weight s
DOOR: in BIT; --door opened or not
ETAJ: out std_logic_vector (12 downto 0):="0000000000001"); --output to LCD
end lift;
architecture mama of lift is
signal directie: bit := '1'; --direction of lift, 1 up / 0 down
signal pozitie: natural := 0; --position of lift, 0-12
signal sus: bit; --up
signal jos: bit; --down
signal UP: std_logic_vector(12 downto 0) :="0000000000000"; --vector for the outside inputs that ask to go up
signal DOWN: std_logic_vector(12 downto 0) :="0000000000000"; --same as above, but down
begin
merge: process (UP, DOWN, pozitie) --process to determine if the lift goes up or down
variable i : std_ulogic; --the vector with the outside inputs has 1 if the button is pressed, 0 otherwise
variable j : std_ulogic;
begin
for i in pozitie+1 to 12 loop
if UP(i) = '1' then
sus <= '1';
end if;
end loop;
for j in pozitie-1 to 0 loop
if DOWN(j) = '1' then
jos <= '1';
end if;
end loop;
end process merge;
conv: process(iUP, iDOWN) --converts input from binary to int
begin
UP(to_integer(unsigned(iUP)))<='1';
DOWN(to_integer(unsigned(iDOWN)))<='1';
end process conv;
moovit: process (UP, DOWN, iBUTTON) --the moving process
variable i : std_ulogic;
begin
if directie='1' then --if direction is up and it has to go up
while sus='1' loop
if CLK'EVENT and CLK='1' and UP(pozitie)='1' then
UP(pozitie)<='0';
DOWN(pozitie)<='0';
end if;
pozitie <= pozitie + 1;
end loop;
else
while jos='1' loop
if CLK'EVENT and CLK='1' and DOWN(pozitie)='1' then
DOWN(pozitie)<='0';
UP(pozitie)<='0';
end if;
pozitie <= pozitie - 1;
end loop;
end if;
end process;
end mama;
答案 0 :(得分:1)
您的代码中有许多内容与综合不兼容。或者至少其中我不确定它是否会起作用。 例如
merge: process (UP, DOWN, pozitie)
[...]
for i in pozitie+1 to 12 loop
if UP(i) = '1' then
您正在使用可变长度的for循环。这在处理器中很容易,但是您正在编写HDL(硬件描述语言):您如何想象使用可变数量的逻辑门可以工作?
在这种情况下,您应该使用一个comperator。 E.g:
if unsigned(iDOWN) < pozitie then
jos <= '1';
然后看看你的计时过程。您似乎知道如何使用CLK'EVENT and CLK='1'
引入时钟。但是您将语句放在 if
语句中,甚至是while
语句中!再说一遍:您希望如何在硬件中实现这一目标?
正常的时钟同步过程如下所示:
clk_process: process(clk)
begin
if rising_edge(clk) then
[synchronous statement]
end if;
end process;
P.S。如果您已使用use ieee.std_logic_unsigned.all;
,请放弃numeric_std
。