使用VHDL的时钟模式（用于综合）

Question

我刚刚开始使用FPGA，并且作为第一个项目，我想与具有特定闭合模式的CMOS检测器接口。

这是来自模拟器的序列：

时间

In terms of frequencies the granulatiry of signal I need is 10ns (I will prescale external clock). And in terms of timings :
Initial states:
- SEL <= 0
- SHR <= 0
- RST <= 1
- TRA <= 0
- SHS <= 0

Timings:
SEL: 500ns / 1 / 5000ns / 0 / 500ns
SHR: 1000ns / 1 / 1000ns / 0 / 4000ns
RST: 600ns / 0 / 4900ns / 1 / 500ns
TRA: 2500ns / 1 / 1000ns / 0 / 2500ns
SHS: 4000ns / 1 / 1000ns / 0 / 1000ns

实际上如何获得这种特定的信号时序（延迟）？ 我正在考虑对每条线使用多个过程，并使用计数器溢出标志上升沿检测来改变电平，这是一种好方法吗？

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计数器VHDL代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity delay_generator is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           delay_cycles : in unsigned(31 downto 0);
           flag : out STD_LOGIC);
end delay_generator;

architecture Behavioral of delay_generator is

signal count : unsigned(31 downto 0) := (others => '0');

begin

process(clk,reset)
begin
    if(reset = '1') then
        flag <= '0';
        count <= (others => '0');
    elsif(rising_edge(clk)) then
    --when the necessary delay is achieved, reset count and set flag high
        if(count = delay_cycles-1) then 
            count <= (others => '0');
            flag <= '1';
        else
            flag <= '0';
            count <= count +1;   --increment counter otherwise.
        end if; 
    end if;

end process;

end Behavioral;