为Synopsys dc_shell分析器启用VHDL标准2008

时间:2018-04-26 07:33:47

标签: vhdl synthesis

我很难通过dc_shell正确分析我的代码是正确的VHDL(2008语言版本)代码。 下面的案例结构有效2008会产生错误

gen1: case myInt generate
   when 0 =>
       ...
   when 1 =>
       ...
   when 2 =>
       ...
  end generate;

我没有在Synopsys设计编译器文档的任何部分找到它所描述的位置以及是否支持它。

错误:

106:gencfg:case nb_elem generate                   ^^^^

[Failure] Syntax error : received 'case'
          while expecting 'postponed'
                       or '(' or 'assert' or 'block' or 'component'
                       or 'configuration' or 'entity' or 'for' or 'if'
                       or 'process' or 'with' or IDENTIFIER or STRING LITERAL  
*** Presto compilation was unsuccessful. ***

VHDL Snippet很简单:

library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

entity demo is

  generic (
    nbelem : positive range 1 to 6:= 6;
    regwid : positive := 14
    );

  port (
    data    : in  std_logic_vector(regwid-1 downto 0);
    app_clk : in  std_logic_vector(nbelem-1 downto 0);
    clk_out : out std_logic
    );

end demo;

architecture rtl of demo is

  constant selwid   : integer   := integer(ceil(log2(real(nbelem))));
  constant tied_up  : std_logic := '1';
  constant tied_low : std_logic := '0';

  signal sel : std_logic_vector(selwid-1 downto 0);

begin  -- architecture rtl

  -- selectors mapping
  -- NOTE: case style is vhdl08
  gen0: block
  begin
    gencfg: case nbelem generate
      when 5|6 =>
    sel <= data(15 downto 13);
      when 4|3 =>
    sel <= data(12 downto 11);
      when 2 =>
    sel <= data(9 downto 9);
      when 1 =>
    sel <= (others => tied_low);
    end generate gencfg;
  end block gen0;


  p0: process(all) is -- vhdl'08 syntax
    variable sel_v : integer;
  begin  -- process p0_b
    sel_v := to_integer(unsigned(sel));
    if (sel_v < nbelem and sel_v > 0) then
      clk_out <= app_clk(sel_v);
    else
      clk_out <= app_clk(0);
    end if;

  end process p0;



end architecture rtl;

1 个答案:

答案 0 :(得分:0)

实际上vhdl&#39; 08是默认设置的,所以没有特定的选项。

Synopsys已经开了一个案例。但他们没有提供任何支持日期。

解决方法是回到vhdl&#39; 87语法。