我正在尝试将ADDR
分配给pcOut
,但是ADDR
在GTKWave中显示为xxxxxxxx
。
这是我的代码:
module processor (
input CLK,
// Memory
input [31:0] DATAOUT, // Memory data out
output [31:0] DATAIN, // Memory data in
output [31:0] ADDR, // Memory address
output WE // Memory write enable
);
wire [3:0] aluSel;
wire [4:0] regSel1, regSel2, regDataSel;
wire regLoad, aluEnable, pcLoad, pcNext;
wire [31:0] regDataIn, regDataOut1, regDataOut2, aluOut, pcOut, pcIn, aluA, aluB;
assign ADDR = pcOut;
controlUnit controlUnit (
.CLK(CLK), // Clock
// Outputs
.memDataOut(DATAOUT),
.regDataOut1(regDataOut1),
.regDataOut2(regDataOut2),
.aluOut(aluOut),
.pcOut(pcOut),
// Load and enable
.pcLoad(pcLoad),
.regLoad(regLoad),
.aluEnable(aluEnable),
.pcNext(pcNext),
// Selects
.aluSel(aluSel),
.regSel1(regSel1),
.regSel2(regSel2),
.regDataSel(regDataSel),
// Inputs
.pcIn(pcIn),
.regDataIn(regDataIn),
.aluA(aluA),
.aluB(aluB),
.memDataIn(DATAIN),
.memAddr(ADDR)
);
datapath datapath (
.pcNext(pcNext),
// Load and enable
.pcLoad(pcLoad),
.regLoad(regLoad),
.aluEnable(aluEnable),
// Selects
.aluSel(aluSel),
.regSel1(regSel1),
.regSel2(regSel2),
.regDataSel(regDataSel),
// Inputs
.regDataIn(regDataIn),
.pcIn(pcIn),
.aluA(aluA),
.aluB(aluB),
// Outputs
.regDataOut1(regDataOut1),
.regDataOut2(regDataOut2),
.aluOut(aluOut),
.pcOut(pcOut)
);
endmodule
有人可以帮忙吗? 预先感谢。
编辑:
pcOut
输出正确的值,但ADDR
未设置相同的值。
编辑2:
这是controlUnit
模块的代码:
module controlUnit (
input CLK,
input [31:0] memDataOut, regDataOut1, regDataOut2, aluOut, pcOut,
output reg [0:0] pcLoad, regLoad, aluEnable, pcNext,
output reg [3:0] aluSel,
output reg [4:0] regSel1, regSel2, regDataSel,
output reg [31:0] pcIn, regDataIn, aluA, aluB, memDataIn, memAddr
);
reg cycle = 0;
wire [10:0] opcode;
wire [4:0] rs1, rs2, rd;
decoder decoder (
.cycle(cycle),
.instruction(memDataOut),
.rs1(rs1),
.rs2(rs2),
.rd(rd),
.opcode(opcode)
);
always @(posedge CLK) begin
case (cycle)
1'b0: begin
regLoad <= 0;
aluEnable <= 0;
pcNext <= 0;
end
1'b1: begin
pcNext <= 1;
case (opcode)
11'b00000110011: begin // Add
regSel1 <= rs1;
regSel2 <= rs2;
regDataSel <= rd;
aluSel <= 0;
aluEnable <= 1;
regDataIn <= aluOut;
regLoad <= 1;
end
11'b10000110011: begin // Sub
end
endcase
end
endcase
cycle <= !cycle;
end
endmodule
答案 0 :(得分:2)
您的controlUnit
似乎没有与memAddr
关联的逻辑,但是memAddr
仍然是controlUnit
的输出。在顶层,您将映射ADDR
移植到.memAddr
,并且您也assign ADDR = pcOut
。您正在尝试在两个不同的位置开车ADDR
。