VHDL中的FSM是Moore还是Mealy?

时间:2018-12-12 17:42:36

标签: vhdl automata

我正在用VHDL编码FSM。特别地,它是同步序列检测器,其在输入中具有8位数字和“第一”,仅在序列的第一个数字期间才必须为“ 1”。输出由解锁和警告组成:如果序列(36,...)是正确的,则unlock ='1',如果序列错误,则警告='1',或者在第一个数字期间first ='1'的顺序。

在VHDL中,我使用两个进程,一个同步,另一个不同步。第二种的简化版本是:

state_register_p : process(clk)
    begin 
        if (clk'EVENT and clk = '1') then
            if(rst = '0') then
                current_state <= S0;

                errors_num <= "00";
                five_cycles <= "000";
                first_error <= '1';
            else
                current_state <= next_state;

                if correct = '0' then
                    errors_num <= errors_num + "01";
                else
                    errors_num <= "00";
                end if;

            end if;

        end if;

end process state_register_p;

combinatorial_logic_p : process(current_state, num_in, first)

    begin       
        unlock <= '0';
        warning <= '0';

        case (current_state) is             
            when S0 =>
                if (to_integer(unsigned(num_in)) = 36) and (first = '1') then
                    next_state <= S1;
                else
                    next_state <= S0;
           when S1 =>
                correct <= '0';
                if (to_integer(unsigned(num_in)) = 19) and (first = '0') and errors_num /= "11" then
                    next_state <= S2;
                elsif first = '1' or errors_num = "11" then
                    next_state <= S6;
                else
                    next_state <= S0;
                end if;

            when S2 =>
                correct <= '0';
                if (to_integer(unsigned(num_in)) = 56)  and (first = '0') then
                    next_state <= S3;
                elsif first = '1' then
                    next_state <= S6;
                else
                    next_state <= S0;
                end if;

            when S3 =>
                correct <= '0';
                if (to_integer(unsigned(num_in)) = 101) and (first = '0') then
                    next_state <= S4;
                elsif first = '1' then
                    next_state <= S6;
                else
                    next_state <= S0;
                end if;

            when S4 =>
                correct <= '0';
                if (to_integer(unsigned(num_in)) = 73) and (first = '0') and (to_integer(unsigned(five_cycles)) = 5) then
                    next_state <= S5;
                    correct <= '1';
                elsif first = '1' then
                    next_state <= S6;
                else
                    next_state <= S0;
                end if;

            when S5 =>
                correct <= '1';
                if to_integer(unsigned(num_in)) = 36 and (first = '1') then
                    next_state <= S1;
                else
                    next_state <= S0;
                end if;

                unlock <= '1';

            when S6 =>
                correct <= '0';
                next_state <= S6; -- default, hold in current state
                warning <= '1';

        end case;               
end process combinatorial_logic_p;

通过在线阅读,我知道在一台Moore机器中,下一个状态仅取决于当前状态,因此输出仅在时钟沿改变,而在Mealy中,其状态也取决于输入,因此当输入改变时其输出可能会改变(即不一定在时钟沿上)。

在我的敏感度列表中,我使用current_state和2个输入(num_in和first),因此可以说我是在描述Mealy机器还是Moore机器,因为我正在等待下一个上升沿来更新输出?

我仍然认为是摩尔,但我不确定。谢谢

1 个答案:

答案 0 :(得分:1)

这是一个摩尔状态机,因为在unlock过程中,输出warningcurrent_state仅取决于combinatorial_logic_p

请注意,errors_num过程中使用了信号five_cyclescombinatorial_logic_p,但是在灵敏度列表中却忘记了。因此,请添加它们,如果使用VHDL-2008,请更改为(all)