摩尔fsm VHDL测试台

Question

你好，我有这个FSM。

我写了VHDL代码：

library ieee;
use ieee.std_logic_1164.all;

entity fsm is
    port(
            clk, reset : in std_logic;
            level : in std_logic;
            Moore_tick: out std_logic
);
end fsm;

architecture rtl of fsm is

    type stateFsm_type is (s1, s2, s3); -- 3 states are required
    signal stateFsm_reg, stateFsm_next : stateFsm_type;

begin
    process(clk, reset)
    begin
        if (reset = '1') then -- go to state zero if reset
            stateFsm_reg <= s1;
        elsif (clk'event and clk = '1') then -- otherwise update the states
            stateFsm_reg <= stateFsm_next;
        else
            null;
        end if;
    end process;

    process(stateFsm_reg, level)
begin
        -- store current state as next
        stateFsm_next <= stateFsm_reg; -- required: when no case statement is satisfied

        Moore_tick <= '0'; -- set tick to zero (so that 'tick = 1' is available for 1 cycle only)
        case stateFsm_reg is
            when s1 => -- if state is zero,
                if level = '1' then  -- and level is 1
                    stateFsm_next <= s2; -- then go to state edge.
                end if;
            when s2 =>
                Moore_tick <= '1'; -- set the tick to 1.
                if level = '1' then -- if level is 1,
                    stateFsm_next <= s3; --go to state one,
                else
                    stateFsm_next <= s1; -- else go to state zero.
                end if;
            when s3 =>
                if level = '0' then -- if level is 0,
                    stateFsm_next <= s1; -- then go to state zero.
                end if;
        end case;
    end process;
end rtl;

所以我编译了代码没有错误。目前，我正在尝试创建一个测试平台，以便能够获得视觉效果，从而确保它可以正常工作。 这是我为测试台编写的代码。

[![library ieee;
use ieee.std_logic_1164.all;

entity fsm_tb is
end fsm_tb;

architecture fsm_arch_tb of fsm_tb is
component fsm is
  port(
        clk, reset : in std_logic;
        level : in std_logic;
        Moore_tick: out std_logic
);
end component;

signal clk: std_logic :='1';
signal reset: std_logic :='0';
signal level: std_logic :='0';
signal Moore_tick: std_logic ;
type stateFsm_type is (s1, s2 , s3 ); -- 3 states are required
signal stateFsm_reg, stateFsm_next : stateFsm_type ;

constant clk_period : time := 1 ns;

begin

cnt_inst : fsm
  port map (
      clk, reset, level, Moore_tick
  );

clk_gen: process is
begin
      clk <= '1';
      wait for clk_period/2;  --for 5 ns signal is '0'.
      clk <= '0';
      wait for clk_period/2;  --for next 5 ns signal is '1'.
end process clk_gen;

trig: process is
begin

          wait for clk_period;
           level<= '1';     
      wait for clk_period;
       reset <= '0' ;
           level <= '1' ;
      wait for clk_period;
           level <= '1' ;
      wait for clk_period;
           level <= '1' ;
      wait for clk_period;
           reset <= '1' ;
      wait for clk_period;
           reset <= '0' ;
       level <= '1' ;
      wait for clk_period;
           level <= '1' ;
      wait for clk_period;
           level <= '1' ;
      wait for clk_period;
           level <= '1' ;


         wait;
end process trig;

end architecture fsm_arch_tb;

但是我在最后的过程中陷入困境。 我正在尝试实现trig process，以便能够看到波形上的所有跃迁

Answer 1

在测试台中，您正在尝试为信号类型 out

分配一个值

删除这些：

Moore_tick <='0';

Moore_tick <='1';