Question

我试图在VHDl中实现一个8位双向移位寄存器，但是它不能正常工作，因为当我用测试台模拟项目时，我最终得到了这个

我正在为每个必须连接到输出E <=（（NO B）AND（NO C））或（C AND（NO D））或（A AND B和C）。

可能是什么问题？没有错误，问题只是我得到的奇怪波形。

我只能使用逻辑门对移位寄存器进行编程。

        LIBRARY IEEE;

        USE IEEE.STD_LOGIC_1164.ALL;
        USE IEEE.STD_LOGIC_ARITH.ALL;
        USE IEEE.STD_LOGIC_UNSIGNED.ALL;

        entity ShiftRegister8Bit is 
        Port   (A : in STD_LOGIC;
                B : in STD_LOGIC;
                C : in STD_LOGIC;
                D : in STD_LOGIC;
                E : in STD_LOGIC_VECTOR(7 downto 0);
                INPUT: in STD_LOGIC_VECTOR(7 downto 0);
                CLK: in STD_LOGIC;
                RESET: in STD_LOGIC;
                EN: in STD_LOGIC;
                MODE: in STD_LOGIC;
                Q: inout STD_LOGIC_VECTOR (7 downto 0));
        end ShiftRegister8Bit;


        architecture Behavioral of ShiftRegister8Bit is

        component Mux21 is 
            Port(Q0: in STD_LOGIC;
                 Q1: in STD_LOGIC;
                 S: out STD_LOGIC;
                 MODE: in STD_LOGIC);
        end component;

        component OneBitReg is 
           Port ( RESET : in STD_LOGIC;
               Q : out STD_LOGIC; 
               D : in STD_LOGIC;
               EN : in STD_LOGIC;
               CLK: in STD_LOGIC);
        end component;

        component F3 is 
            Port(A: in STD_LOGIC;
                B: in STD_LOGIC;
                C: in STD_LOGIC;
                D: in STD_LOGIC;
                E: out STD_LOGIC);
        end component;

        signal muxout: STD_LOGIC_VECTOR(7 downto 0);
        signal regout: STD_LOGIC_VECTOR(7 downto 0);
        signal count: STD_LOGIC_VECTOR(7 downto 0); -- slowed down clock

        begin

            process(CLK)
            begin
                if(RESET='0') then 
                    count <= (others => '0');
               elsif(CLK'event and CLK='1') then
                    count <= count + '1';
               end if;
            end process;
            Q <= count;


        mux0: Mux21 Port map(Q0 => input(0),Q1 => regout(0),S => muxout(0),MODE => MODE);

         mux1: Mux21 Port map(Q0 => input(1),Q1 => regout(1),S => muxout(1),MODE => MODE);  

         mux2: Mux21 Port map(Q0 => input(2),Q1 => regout(2),S => muxout(2),MODE => MODE);  

         mux3: Mux21 Port map(Q0 => input(3),Q1 => regout(3),S => muxout(3),MODE => MODE);  

         mux4: Mux21 Port map(Q0 => input(4),Q1 => regout(4),S => muxout(4),MODE => MODE);                                                                 

         mux5: Mux21 Port map(Q0 => input(5),Q1 => regout(5),S => muxout(5),MODE => MODE);                                                                 

         mux6: Mux21 Port map(Q0 => input(6),Q1 => regout(6),S => muxout(6),MODE => MODE);                                                                 

         mux7: Mux21 Port map(Q0 => input(7),Q1 => regout(7),S => muxout(7),MODE => MODE);                                                                 


        reg0: OneBitReg Port map(D =>muxout(0),Q => regout(0),  CLK => CLK,RESET => RESET,EN => E(0));   

        reg1: OneBitReg Port map(D =>muxout(1),Q => regout(1),  CLK => CLK,RESET => RESET,EN => E(1)); 

        reg2: OneBitReg Port map(D =>muxout(2),Q => regout(2),  CLK => CLK,RESET => RESET,EN => E(2));           

        reg3: OneBitReg Port map(D =>muxout(3),Q => regout(3),  CLK => CLK,RESET => RESET,EN => E(3));           

        reg4: OneBitReg Port map(D =>muxout(4),Q => regout(4),  CLK => CLK,RESET => RESET,EN => E(4));           

        reg5: OneBitReg Port map(D =>muxout(5),Q => regout(5),  CLK => CLK,RESET => RESET,EN => E(5));           

        reg6: OneBitReg Port map(D =>muxout(6),Q => regout(6),  CLK => CLK,RESET => RESET,EN => E(6));           

        reg7: OneBitReg Port map(D =>muxout(7),Q => regout(7),  CLK => CLK,RESET => RESET,EN => E(7));           


        Q <=regout;

        end Behavioral;

OneBitReg

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity OneBitReg is
    Port ( RESET : in STD_LOGIC;
           Q : out STD_LOGIC; 
           D : in STD_LOGIC;
           EN : in STD_LOGIC;
           CLK: in STD_LOGIC);
end OneBitReg;

architecture Behavioral of OneBitReg is

begin
    process(RESET,CLK)
     begin
         if(RESET='1') then
             Q <= '0';
         Elsif(CLK'event and CLK='1') then
             if(EN='1')then
                 Q <=D;
             End if;
         End if;
     End process;

end Behavioral;

Mux21

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mux21 is
    Port(Q0 : in STD_LOGIC;
         Q1: in STD_LOGIC;
         S: out STD_LOGIC;
         MODE: in STD_LOGIC);
end Mux21;

architecture Behavioral of Mux21 is

begin
S <= ((NOT MODE) AND Q0) OR (MODE AND Q1);
end Behavioral;

F3

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity F3 is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           C : in STD_LOGIC;
           D : in STD_LOGIC;
           E: out STD_LOGIC);
end F3;

architecture Behavioral of F3 is

begin
E <=  ((NOT B) AND (NOT C)) OR (C AND (NOT D)) OR (A AND B AND C);
end Behavioral;

测试台

        LIBRARY IEEE;

        USE IEEE.STD_LOGIC_1164.ALL;
        USE IEEE.STD_LOGIC_ARITH.ALL;
        USE IEEE.STD_LOGIC_UNSIGNED.ALL;

        entity ShiftRegister8Bit_tb is
        end;

        architecture bench of ShiftRegister8Bit_tb is 

        component ShiftRegister8Bit is
        Port   (A : in STD_LOGIC;
                B : in STD_LOGIC;
                C : in STD_LOGIC;
                D : in STD_LOGIC;
                E : in STD_LOGIC_VECTOR(7 downto 0);
                INPUT: in STD_LOGIC_VECTOR(7 downto 0);
                CLK: in STD_LOGIC;
                RESET: in STD_LOGIC;
                EN: in STD_LOGIC;
                MODE: in STD_LOGIC;
                Q: inout STD_LOGIC_VECTOR (7 downto 0));
        end component; 

           -- Inputs      
           signal A: STD_LOGIC;
           signal B: STD_LOGIC;
           signal C: STD_LOGIC;
           signal D: STD_LOGIC;
           signal INPUT: STD_LOGIC_VECTOR(7 downto 0); 
           signal E: STD_LOGIC_VECTOR(7 downto 0);   
           signal CLK: STD_LOGIC;
           signal RESET: STD_LOGIC;
           signal EN: STD_LOGIC;
           signal MODE: STD_LOGIC;
               --Outputs  
           signal Q : std_logic_vector(7 downto 0);  

        Begin
        uut: ShiftRegister8Bit port map(  
              A => A,
              B => B,
              C => C,
              D => D,
              CLK => CLK,
              INPUT => INPUT,
              RESET => RESET,
              MODE => MODE,
              EN => EN,
              E => E,
              Q => Q );  

         CLK_process :process
                   begin
                   CLK <= '0';
                   wait for 5 ns;
                   CLK <= '1';
                   wait for 5 ns;
              end process;

        -- Stimulus process
         stim_proc: process
         -- SET THE CLOCK PERIOD:  
        begin
             RESET <= '0';
             EN <= '1';
             MODE <= '0';
             A <= '0';
             B <= '0';
             C <= '0';
             D <= '1';
             wait for 50 ns;
             A <= '0';
             B <= '0';
             C <= '1';
             D <= '1';
             wait for 50 ns;
             A <= '0';
             B <= '1';
             C <= '1';
             D <= '1';
             wait for 50 ns;
             A <= '1';
             B <= '1';
             C <= '1';
             D <= '1';
             wait for 50 ns;
             MODE <= '1';
                  A <= '0';
             B <= '0';
             C <= '0';
             D <= '1';
             wait for 50 ns;
             A <= '0';
             B <= '0';
             C <= '1';
             D <= '1';
             wait for 50 ns;
             A <= '0';
             B <= '1';
             C <= '1';
             D <= '1';
             wait for 50 ns;
             A <= '1';
             B <= '1';
             C <= '1';
             D <= '1';
             wait for 50 ns;
             RESET <= '1';
             EN <= '0';
             wait for 50 ns;
         wait;
         end process;
         END;

在VHDL

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