Question

我正在尝试创建一个10位移位寄存器。但是我一直收到错误

[DRC 23-20]规则违规（NSTD-1）未指定的I / O标准 - 15个逻辑端口中的2个使用I / O标准（IOSTANDARD）值'DEFAULT'，而不是用户指定的特定值。这可能会导致I / O争用或与电路板电源或连接不兼容，从而影响性能，信号完整性或在极端情况下导致设备或其所连接的组件受损。要更正此违规，请指定所有I / O标准。除非所有逻辑端口都定义了用户指定的I / O标准值，否则此设计将无法生成比特流。要允许使用未指定的I / O标准值创建比特流（不推荐），请使用以下命令：set_property SEVERITY {Warning} [get_drc_checks NSTD-1]。注意：使用Vivado运行基础结构（例如，launch_runs Tcl命令）时，将此命令添加到.tcl文件，并将该文件添加为执行运行的write_bitstream步骤的预挂钩。问题端口：Clk，btnu。

每次我都要写比特流。有人可以帮助我指出正确的方向并指出我正在制造的任何其他错误，这将使我的移位寄存器无法正常工作。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity question2 is
Port (
  led: out std_logic_vector (9 downto 0);
  Clk: in std_logic;
  btnu: in std_logic;
  btnL: in std_logic;
  btnR: in std_logic ; 
  btnD: in std_logic;
  btnC: in std_logic 
 );

end question2;

architecture Behavioral of question2 is

  constant active: std_logic :='1';
  constant inactive: std_logic :='0';

  constant step_zero: std_logic_vector(9 downto 0)      :="0000000000";  
  constant step_one: std_logic_vector(9 downto 0)      :="0000000001";
  constant step_two: std_logic_vector(9 downto 0)      :="0000000010"; 
  constant step_three: std_logic_vector(9 downto 0)    :="0000000100";
  constant step_four: std_logic_vector(9 downto 0)     :="0000001000";
  constant step_five: std_logic_vector(9 downto 0)     :="0000010000";
  constant step_six: std_logic_vector(9 downto 0)      :="0000100000";    
  constant step_seven: std_logic_vector(9 downto 0)    :="0001000000";
  constant step_eight: std_logic_vector(9 downto 0)    :="0010000000";
  constant step_nine: std_logic_vector(9 downto 0)     :="0100000000";
  constant step_ten: std_logic_vector(9 downto 0)     :="0100000000";

  signal DataIn:  std_logic_vector (9 downto 0):= "0000000001";  
  signal Load:    std_logic := btnD;
  signal Reset:   std_logic; 
  signal Left:    std_logic:= btnL;
  signal Right:   std_logic:= btnR;
  signal DataOut: std_logic_vector (9 downto 0);
  signal Clear: std_logic:= btnU;
  signal speed_enable: std_logic; 

begin

SpeedControl: process (clk)
                variable counter: integer range 0 to 10000000;
           begin
                speed_enable<=not active;  
                if Reset = Active then
                    counter:= 0; 
                elsif (rising_edge (clk)) then 
                    counter := counter + 1; 
                    if (counter=10000000) then 
                        speed_enable<= Active; 
                        counter:=0; 
                    end if; 
                end if; 
            end process; 

shiftregister: process(speed_enable, clear, DataIn)

    begin
    if speed_enable=active then 
        if clear=active then 
            DataOut (9 downto 0) <= "0000000000"; --(others=>'0'); 
        elsif load = Active then 
            DataOut (9 downto 0) <= DataIn ; 
        elsif Left = Active then 
            DataOut (9 downto 0) <= DataOut(7 downto 0) & "11" ;   
        elsif Right = Active then 
            DataOut (9 downto 0) <= DataOut (9 downto 2) & "11" ;

        end if; 
   end if;  
end process;

LEDSTEP: process(DataOut)
  begin
      if DataOut = "0000000000" then 
            led <= step_zero; 
      elsif DataOut = "0000000001" then
            led <= step_one;
      elsif DataOut = "0000000010" then
            led <= step_two; 
      elsif DataOut = "0000000100" then
           led <= step_three;
      elsif DataOut = "000001000" then
           led <= step_four;
     elsif DataOut = "0000010000" then
           led <= step_five; 
     elsif DataOut = "0000100000" then
           led <= step_six; 
     elsif DataOut = "0001000000" then
           led <= step_seven; 
     elsif DataOut = "0010000000" then
           led <= step_eight;
     elsif DataOut = "0100000000" then
           led <= step_nine; 
     elsif DataOut = "1000000000" then
           led <= step_ten; 

      end if; 
      end process;   

end Behavioral;

Answer 1

如评论中所述，这是您的设计约束的问题。 Xilinx支持answers中概述了该问题的详细描述（以及典型解决方案）。

但是，在此特定实例中，您实际上已为所抱怨的端口（clk和btnU）指定了PACKAGE_PIN和IOSTANDARD约束。问题实际上是由于vhd文件和xdc文件之间的区别（由于是Tcl，区分大小写）。在您的vhd文件中，导致错误的端口是Clk和btnu - 这些在约束文件中不存在。

要解决此问题，请将您的端口声明修改为：

entity question2 is
Port (
  led: out std_logic_vector (9 downto 0);
  clk: in std_logic;
  btnU: in std_logic;
  btnL: in std_logic;
  btnR: in std_logic ; 
  btnD: in std_logic;
  btnC: in std_logic 
 );

end question2;

（相反，您可以修改约束文件，但是您将改变使用的命名约定。）

在here中描述了讨论约束文件中案例敏感性的类似问题。

VHDL 10位移位寄存器

1 个答案: