Question

我正在尝试获得两个输出（pulse(0) and pulse(1)）以提供短暂的一个时钟脉冲。这些脉冲之间的延迟需要通过某个输入值来控制。所以0x1 = 1个时钟周期等。

此刻，一旦触发器打开，它就会一直亮着

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.ipbus.all;

<...snip>


architecture rtl of trig_latency is

signal ack : std_logic;
signal s_level : unsigned(pulse'range);
signal s_level_d1 : std_logic;
signal bit_shift : std_logic_vector(addr_width downto 0);
signal latency: integer:=5;


begin
latency <= to_integer(unsigned(in_data(addr_width -1 downto 0))) when addr_width > 0 else 0;
    process(clk)
        begin
            if rising_edge(clk) then
                if ipbus_in.ipb_strobe='1' and ipbus_in.ipb_write = '1' then
                    s_level <= s_level + 1;
                    s_level_d1<=s_level(s_level'left);
                              else
                               s_level<=(others=>'0);


                end if;

                bit_shift <= bit_shift(bit_shift'high-1 downto 0) & (s_level(s_level'left) and (not s_level_d1));
                ipbus_out.ipb_rdata <= (others => '0');
                ack <= ipbus_in.ipb_strobe and not ack; 

                pulse(0) <= s_level(s_level'left) and (not s_level_d1);
                pulse(1)<=bit_shift(latency);

            end if;

    end process;

  ipbus_out.ipb_ack <= ack;
  ipbus_out.ipb_err <= '0';

end rtl;

Answer 1

为什么你不能完全转移你的位并忽略它们高于N的事实。通常的VHDL移位器使用&将移位寄存器与新值连接：

bit_shift <= bit_shift(bit_shift'high-1 downto 0) & s_level;

这应该可以很好地产生你的移位寄存器。

pulse(1) <= bit_shift(N)应该可以正常工作。

位移寄存器vhdl大小不一

1 个答案: