Question

尝试这样做

parameter integer PRECHARGE_CLOCKS = $ceil(PRECHARGE_NS / CLOCK_PERIOD_NS);

然后在比较中使用该值

if(InitPrechargeCounter < PRECHARGE_CLOCKS - 1)

但是出现此错误

Error (10174): Verilog HDL Unsupported Feature error at Ram.sv(23): system function "$ceil" is not supported for synthesis

有没有办法解决这个问题，以便获得编译时计算出的值？
使用其他语言构造代替parameter？

Answer 1

尝试一下：

参数整数PRECHARGE_CLOCKS =（（（PRECHARGE_NS + CLOCK_PERIOD_NS -1）/ CLOCK_PERIOD_NS））;

它应该像$ ceil一样四舍五入。

Answer 2

I ended up working around this with the following macro, this creates 2 extra parameters for the sake of rounding up, but this is the best solution I've found so far. This is not limited to integer arguments and works with real numbers. I've tested this with Quartus and Modelsim

`define Ceil(ParamName, Expression) \
 parameter ParamName``_F = Expression;\
 parameter integer ParamName``_R = ParamName``_F;\
 parameter integer ParamName = (ParamName``_R == ParamName``_F || ParamName``_R > ParamName``_F) ? ParamName``_R : (ParamName``_R + 1);

And then instead of

 parameter integer AUTOREFRESH_CLOCKS = $ceil(UTOREFRESH_NS/CLOCK_PERIOD_NS);

You would invoke the macro

`Ceil(AUTOREFRESH_CLOCKS, UTOREFRESH_NS/CLOCK_PERIOD_NS)

And this is not both synthesizable in Quartus and works in Modelsim

使用$ ceil在Quartus Prime的SystemVerilog中定义参数

2 个答案: