Question

    library ieee;
    use ieee.std_logic_1164.all;

    entity lab2exercise2 is

    port
    (
    clk : in    std_logic;
    data_in1    : in    std_logic;
    data_in2    : in    std_logic;
    reset   : in    std_logic;
    data_out    : out   std_logic_vector(1 downto 0)
    );

    end lab2exercise2;

    architecture rtl of lab2exercise2 is

    -- Build an enumerated type for the state machine
    type state_type is (a, b, c, d);

    -- Register to hold the current state
    signal state : state_type;
    signal clk_1hz : std_logic:= '0';
    begin
    process(clk)
    variable counter : integer := 0;
    variable edge_toggle : std_logic := '0';
    begin
        if (rising_edge(clk)) then
    counter := counter + 1;
    if (counter = 25000000) then
    edge_toggle := not edge_toggle;
    counter := 0;
    end if;
    end if;
    clk_1hz <= edge_toggle;
    end process;


    process (clk_1hz, reset)
    begin
    if reset = '1' then
    state<= a;
    elsif (rising_edge(clk_1hz)) then
    -- Determine the next state synchronously, based on
    -- the current state and the input
    case state is
    when a=>
    if((data_in1 = '0') & (data_in2 = '0'))then
    state<=a;
    if((data_in1 = '1') & (data_in2 = '0'))then
    state<=a;
    if((data_in1 = '1') & (data_in2 = '1')) then
    state<=a;
    else 
    state<=c;
    end if;
    when b=>
    if ((data_in1 = '0') & (data_in2 = '0')) then
    state<=a;
    else if ((data_in1 = '1') & (data_in2 = '0'))then
    state<=d;
    else if ((data_in1 = '1') & (data_in2 = '1'))then
    state<=d;
    else
    state<=c;
    end if;
    when c=>
    if ((data_in1 = '1') & (data_in2 = '0')) then
    state<=a;
    else if ((data_in1 = '1') & (data_in2 = '1')) then
    state<=a;
    else if ((data_in1 = '0') & (data_in2 = '1')) then
    state<=d;
    else
    state<=b;
    end if;
    when d=>
    if ((data_in1 = '0') & (data_in2 = '1'))then 
    state<=d;
    else if((data_in1 = '1') & (data_in2 = '0')) then 
    state<=d;   
    else if((data_in1 = '1') & (data_in2 = '1')) then
    state<=d;
    else
    state<=b;
    end if;
    end case;

    end if;
    end process;


    -- Determine the output based only on the current state
    -- and the input (do not wait for a clock edge).

    process (state, data_in1, data_in2)
    begin
    case state is
    when a=>
    if((data_in1 = '0') & (data_in2 = '0'))then
    data_out<= "000";
    if((data_in1 = '1') & (data_in2 = '0'))then
    data_out<= "000";
    if((data_in1 = '1') & (data_in2 = '1')) then
    data_out<= "000";
    else 
    data_out<= "010";
    end if;
    when b=>
    if ((data_in1 = '0') & (data_in2 = '0')) then
    data_out<= "000";
    else if ((data_in1 = '1') & (data_in2 = '0'))then
    data_out<= "011";
    else if ((data_in1 = '1') & (data_in2 = '1'))then
    data_out<= "011";
    else
    data_out<= "010";
    end if;
    when c=>
    if ((data_in1 = '1') & (data_in2 = '0')) then
    data_out<= "100";
    else if ((data_in1 = '1') & (data_in2 = '1')) then
    data_out<= "100";
    else if ((data_in1 = '0') & (data_in2 = '1')) then
    data_out<= "111";
    else
    data_out<= "101";
    end if;
    when d=>
    if ((data_in1 = '0') & (data_in2 = '1'))then 
    data_out<= "111";
    else if((data_in1 = '1') & (data_in2 = '0')) then 
    data_out<= "111";   
    else if((data_in1 = '1') & (data_in2 = '1')) then
    data_out<= "111";
    else
    data_out<= "111";
    end if;
    end case;
    end process;

    end rtl;

这是我的代码。我尝试运行它，但总是在行上收到错误10500 “当b =>时，当c =>时，当d =>时”和“结束进程”。如何正确运行代码？这是一台基于Mealy的机器。具有两个D触发器A和B，两个输入x和y的时序电路；并由下面的下一状态和输出方程式指定一个输出z。

A(t +1)=xy’ +xB
B(t +1)=xA+Xb’
z=A

Answer 1

VHDL shutdown /s /f /m \\computername语句的一般语法为：

if

如果您使用if condition1 then ... elsif condition2 then ... elsif condition3 then ... else ... end if;而不是else if，则有多个嵌套的elsif语句，并且您需要的if数量也很多：

end if

注意：

正确缩进代码可使代码（对于您和StackOverflow读者）更具可读性，更易于调试和维护。
问为什么在没有显示错误消息的情况下仍然出错，不是寻求帮助的最佳方法。错误消息通常在这里可以帮助您（或StackOverflow阅读器）了解问题出在哪里。掩盖它就像告诉医生很痛，但没有告诉他在哪里。
您也许可以访问Asking section，以更好地理解如何提出好的问题，尤其是Minimal, Complete, and Verifiable example (MCVE)是什么。

带两个输入和一个输出的Mealy机器的VHDL代码

1 个答案: