我的问题是我有两个向量，例如A和B.当时钟为1时，我必须选择A向量的第一个元素A（0），当时钟为零时，B（0） ，以及随后的A（1），B（1），A（2），B（2）......
我遇到一些问题的实际代码是：
----------------------顶级实体--------------
library ieee;
use ieee.std_logic_1164.all;
entity topentity is
generic
(
DATA_WIDTH : natural := 8
);
port
(
clk : in std_logic;
enable : in std_logic;
final_out : out std_logic_vector(2*(DATA_WIDTH-1) downto 0)
);
end entity ;
architecture top of topentity is
signal A,B : std_logic_vector((DATA_WIDTH-1) downto 0);
component basic_shift_register_with_multiple_taps is
generic
(
DATA_WIDTH : natural := 8
);
port
(
clk : in std_logic;
enable : in std_logic;
sr_one : in std_logic_vector((DATA_WIDTH-1) downto 0);
sr_two : in std_logic_vector((DATA_WIDTH-1) downto 0);
sr_out : out std_logic_vector(2*(DATA_WIDTH-1) downto 0)
);
end component;
begin
A <= "01010101";
B <= "10101010";
as: basic_shift_register_with_multiple_taps port map (clk,enable,A,B, final_out(2*(DATA_WIDTH-1) downto 0));
end top;
-------------------元器件-----------------
library ieee;
use ieee.std_logic_1164.all;
entity basic_shift_register_with_multiple_taps is
generic
(
DATA_WIDTH : natural := 8
);
port
(
clk : in std_logic;
enable : in std_logic;
sr_one : in std_logic_vector((DATA_WIDTH-1) downto 0);
sr_two : in std_logic_vector((DATA_WIDTH-1) downto 0);
sr_out : out std_logic_vector(2*(DATA_WIDTH-1) downto 0)
);
end entity ;
architecture rtl of basic_shift_register_with_multiple_taps is
signal sig_out :std_logic_vector(2*(DATA_WIDTH-1) downto 0);
variable count : integer := 0;
variable count1 : integer := 0;
begin
process (clk,enable,sr_one,sr_two,sig_out)
begin
if(enable = '0' or count = 16) then
count := 0;
count1 := 0;
else
if (clk'event and clk='1') then
sig_out(count) <= sr_one(count1);
count := count + 1;
else --if (clk'event and clk='0') then--
sig_out(count) <= sr_two(count1);
count := count + 1;
end if;
end if;
count1 := count1 + 1;
end process;
sr_out <= sig_out;
end rtl;
-------这是一个时钟输入代码这里错误我无法解决---------
Info: Running Quartus Prime Analysis & Synthesis Info: Version
16.1.1 Build 200 11/30/2016 SJ Lite Edition Info: Processing started: Tue Jan 10 11:44:53 2017 Info: Command: quartus_map
--read_settings_files=on --write_settings_files=off teste -c teste Warning (18236): Number of processors has not been specified which
may cause overloading on shared machines. Set the global assignment
NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best
performance. Info (20030): Parallel compilation is enabled and will
use 2 of the 2 processors detected Info (12021): Found 2 design
units, including 1 entities, in source file vhdl1.vhd Info (12022):
Found design unit 1: basic_shift_register_with_multiple_taps-rtl
Info (12023): Found entity 1:
basic_shift_register_with_multiple_taps Info (12021): Found 2 design
units, including 1 entities, in source file teste.vhd Info (12022):
Found design unit 1: topentity-top Info (12023): Found entity 1:
topentity Info (12127): Elaborating entity "topentity" for the top
level hierarchy Info (12128): Elaborating entity
"basic_shift_register_with_multiple_taps" for hierarchy
"basic_shift_register_with_multiple_taps:as" Error (10818): Can't
infer register for "sig_out[0]" at Vhdl1.vhd(41) because it does not
hold its value outside the clock edge Info (10041): Inferred latch
for "sig_out[0]" at Vhdl1.vhd(33) Error (10818): Can't infer register
for "sig_out[1]" at Vhdl1.vhd(41) because it does not hold its value
outside the clock edge Info (10041): Inferred latch for "sig_out[1]"
at Vhdl1.vhd(33) Error (10818): Can't infer register for "sig_out[2]"
at Vhdl1.vhd(41) because it does not hold its value outside the clock
edge Info (10041): Inferred latch for "sig_out[2]" at Vhdl1.vhd(33)
Error (10818): Can't infer register for "sig_out[3]" at Vhdl1.vhd(41)
because it does not hold its value outside the clock edge Info
(10041): Inferred latch for "sig_out[3]" at Vhdl1.vhd(33) Error
(10818): Can't infer register for "sig_out[4]" at Vhdl1.vhd(41)
because it does not hold its value outside the clock edge Info
(10041): Inferred latch for "sig_out[4]" at Vhdl1.vhd(33) Error
(10818): Can't infer register for "sig_out[5]" at Vhdl1.vhd(41)
because it does not hold its value outside the clock edge Info
(10041): Inferred latch for "sig_out[5]" at Vhdl1.vhd(33) Error
(10818): Can't infer register for "sig_out[6]" at Vhdl1.vhd(41)
because it does not hold its value outside the clock edge Info
(10041): Inferred latch for "sig_out[6]" at Vhdl1.vhd(33) Error
(10818): Can't infer register for "sig_out[7]" at Vhdl1.vhd(41)
because it does not hold its value outside the clock edge Info
(10041): Inferred latch for "sig_out[7]" at Vhdl1.vhd(33) Error
(10818): Can't infer register for "sig_out[8]" at Vhdl1.vhd(41)
because it does not hold its value outside the clock edge Info
(10041): Inferred latch for "sig_out[8]" at Vhdl1.vhd(33) Error
(10818): Can't infer register for "sig_out[9]" at Vhdl1.vhd(41)
because it does not hold its value outside the clock edge Info
(10041): Inferred latch for "sig_out[9]" at Vhdl1.vhd(33) Error
(10818): Can't infer register for "sig_out[10]" at Vhdl1.vhd(41)
because it does not hold its value outside the clock edge Info
(10041): Inferred latch for "sig_out[10]" at Vhdl1.vhd(33) Error
(10818): Can't infer register for "sig_out[11]" at Vhdl1.vhd(41)
because it does not hold its value outside the clock edge Info
(10041): Inferred latch for "sig_out[11]" at Vhdl1.vhd(33) Error
(10818): Can't infer register for "sig_out[12]" at Vhdl1.vhd(41)
because it does not hold its value outside the clock edge Info
(10041): Inferred latch for "sig_out[12]" at Vhdl1.vhd(33) Error
(10818): Can't infer register for "sig_out[13]" at Vhdl1.vhd(41)
because it does not hold its value outside the clock edge Info
(10041): Inferred latch for "sig_out[13]" at Vhdl1.vhd(33) Error
(10818): Can't infer register for "sig_out[14]" at Vhdl1.vhd(41)
because it does not hold its value outside the clock edge Info
(10041): Inferred latch for "sig_out[14]" at Vhdl1.vhd(33) Info
(10041): Inferred latch for "count1[0]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[1]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[2]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[3]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[4]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[5]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[6]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[7]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[8]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[9]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[10]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[11]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[12]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[13]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[14]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[15]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[16]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[17]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[18]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[19]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[20]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[21]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[22]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[23]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[24]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[25]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[26]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[27]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[28]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[29]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[30]" at Vhdl1.vhd(37) Info
(10041): Inferred latch for "count1[31]" at Vhdl1.vhd(37) Error
(10818): Can't infer register for "count[0]" at Vhdl1.vhd(41) because
it does not hold its value outside the clock edge Error (10818):
Can't infer register for "count[1]" at Vhdl1.vhd(41) because it does
not hold its value outside the clock edge Error (10818): Can't infer
register for "count[2]" at Vhdl1.vhd(41) because it does not hold its
value outside the clock edge Error (10818): Can't infer register for
"count[3]" at Vhdl1.vhd(41) because it does not hold its value
outside the clock edge Error (12152): Can't elaborate user hierarchy
"basic_shift_register_with_multiple_taps:as" Error: Quartus Prime
Analysis & Synthesis was unsuccessful. 20 errors, 1 warning Error:
Peak virtual memory: 726 megabytes Error: Processing ended: Tue Jan
10 11:45:11 2017 Error: Elapsed time: 00:00:18 Error: Total CPU
time (on all processors): 00:00:41
答案 0 :(得分：0)
我建议描述两组寄存器，一组仅在上升沿工作，另一组仅在下降沿工作，并根据clk的电平将寄存器复用到输出。我没有看到你需要count1变量的任何理由，所以我删除了它。最后，我建议避免异步重置，除非你真的需要重置为异步。 我只编译了以下代码，没有执行功能模拟，所以我不知道如果代码真的做了你想要的东西。但它可能是进一步社区讨论的起点。
library ieee;
use ieee.std_logic_1164.all;
entity basic_shift_register_with_multiple_taps is
generic
(
DATA_WIDTH : natural := 8
);
port
(
clk : in std_logic;
enable : in std_logic;
sr_one : in std_logic_vector((DATA_WIDTH-1) downto 0);
sr_two : in std_logic_vector((DATA_WIDTH-1) downto 0);
sr_out : out std_logic_vector(2*(DATA_WIDTH-1) downto 0)
);
end entity ;
architecture rtl of basic_shift_register_with_multiple_taps is
signal sig_out_one :std_logic_vector(2*(DATA_WIDTH-1) downto 0);
signal sig_out_two :std_logic_vector(2*(DATA_WIDTH-1) downto 0);
begin
process (clk)
variable count : integer := 0;
begin
if (clk'event and clk='1') then
if enable = '0' then
count := 0;
else
sig_out_one(2*count) <= sr_one(count);
if count<sr_one'high then
count := count + 1;
else
count := 0;
end if;
end if;
end if;
end process;
process (clk)
variable count : integer := 0;
begin
if (clk'event and clk='0') then
if enable = '0' then
count := 0;
else
sig_out_two(2*count+1) <= sr_two(count);
if count<sr_two'high then
count := count + 1;
else
count := 0;
end if;
end if;
end if;
end process;
with clk select
sr_out <= sig_out_one when '1',
sig_out_two when others;
end rtl;