我正在尝试使用verilog HDL在ALTERA DE2板上实现猜谜游戏。 Player1选择0到7之间的数字，Player2猜测数字，反之亦然，直到达到score3。 但似乎提交按钮和计数按钮不能同时工作。如果我注释掉提交或计数中的一个，则另一个工作正常。完整代码如下所示。
module test2 (
input [2:0] answer_pin,
input count,
input submit,
input reset,
output reg [6:0] phase,
output reg [6:0] answer,
output reg [6:0] red_state,
output reg [6:0] red_score,
output reg [6:0] blue_state,
output reg [6:0] blue_score
);
wire trig = (count & submit);
reg [2:0] count_value;
reg [1:0] phase_value;
reg red_state_value;
reg [1:0] red_score_value;
reg blue_state_value;
reg [1:0] blue_score_value;
always @(negedge reset or negedge trig)
begin
if (~reset) begin
phase_value <= 2'b01;
blue_state_value <= 1'b0;
blue_score_value <= 2'b00;
red_state_value <= 1'b1;
red_score_value <= 2'b00;
count_value <= 3'b000;
end
else if(~submit) begin
if(phase_value == 2'b01) begin
phase_value <= 2'b10;
end
else if(phase_value == 2'b00) begin
phase_value <= 2'b00;
end
else begin
if(red_state_value == 2'b01) begin
if(answer_pin == count_value) begin
if(blue_score_value == 2'b10) begin
blue_score_value <= blue_score_value + 1'b1;
phase_value <= 2'b00;
end
else begin
red_state_value <= 1'b0;
blue_state_value <= 1'b1;
blue_score_value <= blue_score_value + 1'b1;
count_value <= 3'b000;
phase_value <= 2'b01;
end
end
else begin
if(red_score_value == 2'b10) begin
red_score_value <= red_score_value + 1'b1;
phase_value <= 2'b00;
end
else begin
red_state_value <= 1'b0;
blue_state_value <= 1'b1;
red_score_value <= red_score_value + 1'b1;
count_value <= 3'b000;
phase_value <= 2'b01;
end
end
else begin
if(answer_pin == count_value) begin
if(red_score_value == 2'b10) begin
red_score_value <= red_score_value + 1'b1;
phase_value <= 2'b00;
end
else begin
red_state_value <= 1'b1;
blue_state_value <= 1'b0;
blue_score_value <= blue_score_value + 1'b1;
count_value <= 3'b000;
phase_value <= 2'b01;
end
end
else begin
if(blue_score_value == 2'b10) begin
blue_score_value <= blue_score_value + 1'b1;
phase_value <= 2'b00;
end
else begin
red_state_value <= 1'b1;
blue_state_value <= 1'b0;
blue_score_value <= blue_score_value + 1'b1;
count_value <= 3'b000;
phase_value <= 2'b01;
end
end
end
end
end
else begin
if (phase_value!=2'b00) begin
if (phase_value == 2'b01) begin
if (count_value == 3'b111) begin
if(red_state_value == 1'b1) begin
if(blue_score_value == 2'b10) begin
blue_score_value <= blue_score_value + 1'b1;
phase_value <= 2'b00;
end
else begin
blue_state_value <= 1'b1;
red_state_value <= 1'b0;
blue_score_value <= blue_score_value + 1'b1;
count_value <= 3'b000;
end
end
else begin
if(red_score_value == 2'b10) begin
red_score_value <= red_score_value + 1'b1;
phase_value <= 2'b00;
end
else begin
red_state_value <= 1'b1;
blue_state_value <= 1'b0;
red_score_value <= red_score_value + 1'b1;
count_value <= 3'b000;
end
end
end
else
count_value <= count_value + 1'b1;
end
end
end
end
always @(*)
begin
case(answer_pin)
3'b000: answer=7'b1000000;
3'b001: answer=7'b1111001;
3'b010: answer=7'b0100100;
3'b011: answer=7'b0110000;
3'b100: answer=7'b0011001;
3'b101: answer=7'b0010010;
3'b110: answer=7'b0000010;
3'b111: answer=7'b1011000;
default: answer=7'b1000000;
endcase
case(red_state_value)
1'b1: red_state = 7'b0111111;
1'b0: red_state = 7'b1111111;
default: red_state=7'b0111111;
endcase
case(blue_state_value)
1'b1: blue_state = 7'b0111111;
1'b0: blue_state = 7'b1111111;
default: blue_state = 7'b1111111;
endcase
case(red_score_value)
2'b00: red_score = 7'b1000000;
2'b01: red_score = 7'b1111001;
2'b10: red_score = 7'b0100100;
2'b11: red_score = 7'b0110000;
default: red_score= 7'b1000000;
endcase
case(blue_score_value)
2'b00: blue_score = 7'b1000000;
2'b01: blue_score = 7'b1111001;
2'b10: blue_score = 7'b0100100;
2'b11: blue_score = 7'b0110000;
default: blue_score= 7'b1000000;
endcase
case(phase_value)
2'b00: phase = 7'b1000000;
2'b01: phase = 7'b1111001;
2'b10: phase = 7'b0100100;
default: phase= 7'b1111001;
endcase
end
endmodule
答案 0 :(得分：0)
end。尽量在缩进中保持一致。
没有查看代码本身，因此可能仍无法正常工作。
module test2 (
input [2:0] answer_pin,
input count,
input submit,
input reset,
output reg [6:0] phase,
output reg [6:0] answer,
output reg [6:0] red_state,
output reg [6:0] red_score,
output reg [6:0] blue_state,
output reg [6:0] blue_score
);
wire trig = (count & submit);
reg [2:0] count_value;
reg [1:0] phase_value;
reg red_state_value;
reg [1:0] red_score_value;
reg blue_state_value;
reg [1:0] blue_score_value;
always @(negedge reset or negedge trig) begin
if (~reset) begin
phase_value <= 2'b01;
blue_state_value <= 1'b0;
blue_score_value <= 2'b00;
red_state_value <= 1'b1;
red_score_value <= 2'b00;
count_value <= 3'b000;
end else if(~submit) begin
if(phase_value == 2'b01) begin
phase_value <= 2'b10;
end else if(phase_value == 2'b00) begin
phase_value <= 2'b00;
end else begin
if(red_state_value == 2'b01) begin
if(answer_pin == count_value) begin
if(blue_score_value == 2'b10) begin
blue_score_value <= blue_score_value + 1'b1;
phase_value <= 2'b00;
end else begin
red_state_value <= 1'b0;
blue_state_value <= 1'b1;
blue_score_value <= blue_score_value + 1'b1;
count_value <= 3'b000;
phase_value <= 2'b01;
end
end else begin
if(red_score_value == 2'b10) begin
red_score_value <= red_score_value + 1'b1;
phase_value <= 2'b00;
end else begin
red_state_value <= 1'b0;
blue_state_value <= 1'b1;
red_score_value <= red_score_value + 1'b1;
count_value <= 3'b000;
phase_value <= 2'b01;
end
end
end else begin //added an end here
if(answer_pin == count_value) begin
if(red_score_value == 2'b10) begin
red_score_value <= red_score_value + 1'b1;
phase_value <= 2'b00;
end else begin
red_state_value <= 1'b1;
blue_state_value <= 1'b0;
blue_score_value <= blue_score_value + 1'b1;
count_value <= 3'b000;
phase_value <= 2'b01;
end
end else begin
if(blue_score_value == 2'b10) begin
blue_score_value <= blue_score_value + 1'b1;
phase_value <= 2'b00;
end else begin
red_state_value <= 1'b1;
blue_state_value <= 1'b0;
blue_score_value <= blue_score_value + 1'b1;
count_value <= 3'b000;
phase_value <= 2'b01;
end
end
end
end
end else begin
if (phase_value!=2'b00) begin
if (phase_value == 2'b01) begin
if (count_value == 3'b111) begin
if(red_state_value == 1'b1) begin
if(blue_score_value == 2'b10) begin
blue_score_value <= blue_score_value + 1'b1;
phase_value <= 2'b00;
end else begin
blue_state_value <= 1'b1;
red_state_value <= 1'b0;
blue_score_value <= blue_score_value + 1'b1;
count_value <= 3'b000;
end
end else begin
if(red_score_value == 2'b10) begin
red_score_value <= red_score_value + 1'b1;
phase_value <= 2'b00;
end else begin
red_state_value <= 1'b1;
blue_state_value <= 1'b0;
red_score_value <= red_score_value + 1'b1;
count_value <= 3'b000;
end
end
end else begin
count_value <= count_value + 1'b1;
end
end
end
end
end
end
always @(*) begin
case(answer_pin)
3'b000: answer=7'b1000000;
3'b001: answer=7'b1111001;
3'b010: answer=7'b0100100;
3'b011: answer=7'b0110000;
3'b100: answer=7'b0011001;
3'b101: answer=7'b0010010;
3'b110: answer=7'b0000010;
3'b111: answer=7'b1011000;
default: answer=7'b1000000;
endcase
case(red_state_value)
1'b1: red_state = 7'b0111111;
1'b0: red_state = 7'b1111111;
default: red_state=7'b0111111;
endcase
case(blue_state_value)
1'b1: blue_state = 7'b0111111;
1'b0: blue_state = 7'b1111111;
default: blue_state = 7'b1111111;
endcase
case(red_score_value)
2'b00: red_score = 7'b1000000;
2'b01: red_score = 7'b1111001;
2'b10: red_score = 7'b0100100;
2'b11: red_score = 7'b0110000;
default: red_score= 7'b1000000;
endcase
case(blue_score_value)
2'b00: blue_score = 7'b1000000;
2'b01: blue_score = 7'b1111001;
2'b10: blue_score = 7'b0100100;
2'b11: blue_score = 7'b0110000;
default: blue_score= 7'b1000000;
endcase
case(phase_value)
2'b00: phase = 7'b1000000;
2'b01: phase = 7'b1111001;
2'b10: phase = 7'b0100100;
default: phase= 7'b1111001;
endcase
end
endmodule