verilog敏感列表混淆

Question

我正在尝试制作内存单元，它有重置信号来清除内存。我试图保持该区域尽可能低，从而避免/ while循环。我写的代码，只清除内存中的第一个条目。我有另一个约束，我无法添加额外的输入信号。通过调试我发现在第一次清除之后总是阻塞不执行。我相信这是灵敏度列表的问题。任何提示都会有所帮助。

module RJMemoryR(Start, WriteEnableRJ, WBaseAddressRJ, RBaseAddressRJ, DataIn, DataOut);

input Start, WriteEnableRJ; 
input [3:0]WBaseAddressRJ, RBaseAddressRJ; // WBaseAddress - write add, RBaseAddress - read add
input [7:0] DataIn;
output [7:0]DataOut;
reg [4:0]i=5'b01111; //counter for 16 values
reg j=0; // temp flag
reg [7:0]RJMem[0:15]; // 8 bit wide 16 deep memory

always @(posedge WriteEnableRJ or posedge Start or j==1)
    begin
    if(j==1)
        begin
            if (i==0)
                begin
                j=0;
                end
            else 
                begin
                RJMem[i]=0;
                i=i-1;
                end
        end
    else if(Start)  
        begin
        j=1;
        end
    else 
        RJMem[WBaseAddressRJ] = DataIn;
    end
assign DataOut = RJMem[RBaseAddressRJ];
endmodule 

这是我用来测试的测试平台。

module mem_tb;

    // Inputs
    reg Start;
    reg WriteEnableRJ;
    reg [3:0] WBaseAddressRJ;
    reg [3:0] RBaseAddressRJ;
    reg [7:0] DataIn;
    reg clk;
    // Outputs
    wire [7:0] DataOut;
    reg [4:0] i;
    // Instantiate the Unit Under Test (UUT)
    RJMemoryR uut (
        .Start(Start), 
        .WriteEnableRJ(WriteEnableRJ), 
        .WBaseAddressRJ(WBaseAddressRJ), 
        .RBaseAddressRJ(RBaseAddressRJ), 
        .DataIn(DataIn), 
        .DataOut(DataOut)
    );

    initial begin
        // Initialize Inputs
        Start = 0;
        WriteEnableRJ = 0;
        WBaseAddressRJ = 0;
        RBaseAddressRJ = 0;
        DataIn = 0;
        clk=0;
        // Wait 100 ns for global reset to finish
      #100;  
        // Add stimulus here
    for (i=0;i<16;i=i+1)
      begin
      #10 WriteEnableRJ=1;
      WBaseAddressRJ =i;
      DataIn=DataIn+4'hf;
      #10 WriteEnableRJ=0;
      end
     #100; 
    Start=1;  
    end
endmodule