如何在VHDL中连接两个模块？

Question

我有两个模块，mod1和mod2。我想将mod1连接到mod2，因此x1和y1输入与x2和y2输入相同。到目前为止，我已经做到了这一点，但我不知道下一步该怎么做。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity modl is
    Port ( x1 : in  STD_LOGIC;
           y1 : in  STD_LOGIC;
           f1 : out  STD_LOGIC);
end modl;

architecture Behavioral of modl is


begin
    f1 <= NOT x1 and y1;

end Behavioral;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mod2 is
    Port ( x2 : in  STD_LOGIC;
           y2 : in  STD_LOGIC;
              z2 : in  STD_LOGIC;
           f2 : out  STD_LOGIC);
end mod2;

architecture Behavioral of mod2 is

    component mod1
    Port( x1 : in STD_LOGIC;
            y1 : in STD_LOGIC;
            f1 : out STD_LOGIC);
    end component;

    signal sign1: STD_LOGIC;


begin
    f2 <= x2 and y2 and z2;

end Behavioral;