Question

这是我的16位MIPS的控制单元，我试图将alucontrol连接到alu单元操作码，但由于它是输出和alu单元操作输入我使用信号opsignal，代码没有给出语法错误但是我在下面提到了这个警告。

我是新手，即使我实际连接它，我也不知道如何将我的aluunit连接到控制单元。另外如果我没有使用功能，A和B所以它将以相同的逻辑运行，对吧？我在端口映射中提到了这些输入和输出，但它显示错误，因为它们是开放端口。使用'open'并没有解决问题所以我只是删除它们，它是否会影响我的代码？警告太多了。我只是不知道如何解决它们

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity controlunit is 
  Port ( opcode : in  STD_LOGIC_VECTOR (2 downto 0);
         --zero : in  STD_LOGIC;
         w_en : out  STD_LOGIC;
         regdst : out  STD_LOGIC;
         alusrc : out  STD_LOGIC;
         --branch : out  STD_LOGIC;
         memwrite : out  STD_LOGIC;
         memtoreg : out  STD_LOGIC;
         alucontrol : out  STD_LOGIC_VECTOR (1 downto 0);
         pcsrc : out  STD_LOGIC);
end controlunit;

architecture Behavioral of controlunit is

  component maindecoder is
    Port ( opcode : in  STD_LOGIC_VECTOR (2 downto 0);
           w_en : out  STD_LOGIC;
           regdst : out  STD_LOGIC;
           alusrc : out  STD_LOGIC;
           branch : out  STD_LOGIC;
           memwrite : out  STD_LOGIC;
           memtoreg : out  STD_LOGIC
           --aluop : out  STD_LOGIC_VECTOR (1 downto 0)
         );
  end component;

  component alu is
    Port ( --clk: in STD_LOGIC;
           --A : in  STD_LOGIC_VECTOR (15 downto 0);
           --B : in  STD_LOGIC_VECTOR (15 downto 0);
           --funct: in STD_LOGIC;
           op: in STD_LOGIC_VECTOR (1 downto 0);
           zero  : out std_logic;
           Result : out  STD_LOGIC_VECTOR (15 downto 0));    
  end component;

  --signal alusig: STD_LOGIC_VECTOR (1 downto 0);
  signal opsignal: STD_LOGIC_VECTOR (1 downto 0);
  signal branch: STD_LOGIC;
  signal zero: STD_logic;

begin

  -- instantiate maindecoder
  decoder: maindecoder port map (opcode => opcode, w_en => w_en,
           regdst => regdst, alusrc => alusrc, branch => branch, memwrite => memwrite, memtoreg => memtoreg);

  aluunit: alu port map (op => opsignal, zero => zero);

  alucontrol <= opsignal;

  pcsrc <= branch and zero;

end Behavioral;


WARNING:Xst:753 - "E:/Xilinx Projects/controlunit/controlunit.vhd" line 46: Unconnected output port 'aluop' of component 'maindecoder'.
WARNING:Xst:753 - "E:/Xilinx Projects/controlunit/controlunit.vhd" line 49: Unconnected output port 'Result' of component 'alu'.
WARNING:Xst:752 - "E:/Xilinx Projects/controlunit/controlunit.vhd" line 49: Unconnected input port 'clk' of component 'alu' is tied to default value.
WARNING:Xst:752 - "E:/Xilinx Projects/controlunit/controlunit.vhd" line 49: Unconnected input port 'A' of component 'alu' is tied to default value.
WARNING:Xst:752 - "E:/Xilinx Projects/controlunit/controlunit.vhd" line 49: Unconnected input port 'B' of component 'alu' is tied to default value. 
WARNING:Xst:752 - "E:/Xilinx Projects/controlunit/controlunit.vhd" line 49: Unconnected input port 'funct' of component 'alu' is tied to default value.
WARNING:Xst:653 - Signal <opsignal> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:1290 - Hierarchical block <aluunit> is unconnected in block <controlunit>. It will be removed from the design.

alu的代码：

   library IEEE;
   use IEEE.STD_LOGIC_1164.ALL;
   use IEEE.std_logic_unsigned.all;
   use ieee.std_logic_arith.all;

  entity alu is 
  Port ( clk: in STD_LOGIC;
          A : in  STD_LOGIC_VECTOR (15 downto 0);
       B : in  STD_LOGIC_VECTOR (15 downto 0);
          funct: in STD_LOGIC;
          op: in STD_LOGIC_VECTOR (1 downto 0);
          zero  : out std_logic;
       Result : out  STD_LOGIC_VECTOR (15 downto 0));

  end alu;

  architecture Behavioral of alu is
begin
 process (clk, op, funct, A, B)
 begin
  if (clk'event and clk = '1') then
    case op is
        when "00" => Result <= A+B;
        when "01" => Result <= A-B;
        when "10" => case funct is 
                        when '0' => Result <= A+B;
                        when '1' => Result <= A-B;
                        when others => null;
                        end case;
        when others => null;
    end case;
    end if;
end process;
    process (A,B) begin
        if (A = B) then
        zero <= '1';
        else zero <= '0';
        end if;
    end process;
   end;

maindecoder的代码

   ibrary IEEE;
   use IEEE.STD_LOGIC_1164.ALL;
   use IEEE.NUMERIC_STD.ALL;

   entity maindecoder is
   Port ( opcode : in  STD_LOGIC_VECTOR (2 downto 0);
       w_en : out  STD_LOGIC;
       regdst : out  STD_LOGIC;
       alusrc : out  STD_LOGIC;
       branch : out  STD_LOGIC;
       memwrite : out  STD_LOGIC;
       memtoreg : out  STD_LOGIC;
       aluop : out  STD_LOGIC_VECTOR (1 downto 0));
  end maindecoder;

  architecture Behavioral of maindecoder is
  signal control: std_logic_vector (7 downto 0);
  begin
    process (opcode)
begin
    case opcode is
        when "000" => control <= "11000010"; -- R-type
        when "001" => control <= "10100100"; --lw
        when "010" => control <= "00101000"; --sw
        when "011" => control <= "00010001";--beq
        when others => control<= "--------";        --illegal opcode
    end case;
end process;

w_en    <= control(7);
regdst  <= control(6);
alusrc  <= control(5);
branch  <= control(4);
memwrite <= control(3);
memtoreg <= control(2);
aluop       <= control(1 downto 0);

   end Behavioral;

Answer 1

警告：Xst：753 - “E：/ Xilinx Projects / controlunit / controlunit.vhd”第46行：组件'maindecoder'的未连接输出端口'aluop'。

这里的问题正是它所说的（你没有连接输出，这不是一个错误），但它与更严重的错误有关：

警告：Xst：653 - 信号＆lt; opsignal＆gt;使用但从未分配。此无源信号将自动连接到值00。

您可能打算将opsignal映射到aluop上的maindecoder输出。

警告：Xst：753 - “E：/ Xilinx Projects / controlunit / controlunit.vhd”第49行：组件'alu'的未连接输出端口'Result'。

再次，正是它所说的。您确定不想连接Result吗？

其余的错误表明你还有一些其他相当严重的问题，即你已经将一堆输入保持未连接状态 - 你已经在alu的组件声明中注释掉了一堆端口而没有映射它们。为什么？请注意，这些端口对于alu的操作非常关键 - 如果没有至少其中一些，它实际上不会做任何事情。

（适用编辑）

Re：您的评论“我使用了一个信号，因为我无法将输出映射到输入。”：

op是alu的输入，因为alu“以某种方式”读取“它。 alu不生成该值或驱动该端口 - 它必须来自其他地方，可能在您在此处发布的代码之外。因此，试图从alu获取其价值是没有意义的。您需要确定该控件的源是什么。如果它是maindecoder，那么你可以从该组件的输出中组合它，但我不确定这是否是你需要的。

麻烦端口映射两个模块在一个

1 个答案: