将这些模块从verilog转换为VHDL

Question

请任何人帮助我将以下Verilog转换为vhdl。谢谢。

module adder(a,b,out); //adder

input [31:0] a,b; //inputs
output [31:0] out; //outputs
reg [31:0] out;
always @(a or b) begin 
    out = a+b;
end 
endmodule

Answer 1

LIBRARY ieee; 
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity adder is 
  PORT ( 
    a : in std_logic_vector(31 downto 0);
    b : in std_logic_vector(31 downto 0); 
    regout : out std_logic_vector (31 downto 0) 
); 
end adder; 

ARCHITECTURE adder_arch of adder is 
begin 

regout <= std_logic_vector(unsigned(a) + unsigned(b));

end adder_arch;