Verilog根据输入选择位

时间:2018-02-25 22:32:21

标签: verilog

我正在编写一个行为verilog模块,其中根据其中一个输入变量选择不同的位。我编写了以下代码来引用D向量中的3-S位置:

module Part4(input [3:0] D, input [1:0] S, output F);
    always @(D, S)
        F = D[3-S];
endmodule

这会产生以下错误:"错误:HDLC编译器:247 - " Part4.v"第5行参考标量线' F'不是法律规则或变量左值 错误:HDLC编译器:44 - " Part4.v"第5行阻止分配的非法左侧"

如何根据输入S选择不同的位?

1 个答案:

答案 0 :(得分:2)

如果Fwire,那么您无法在assign块内always @ reg。要么将其更改为always @,要么在module Part4(input [3:0] D, input [1:0] S, output F); assign F = D[3-S]; endmodule 块之外进行分配,如下所示:

import sys
if 3 == sys.version_info[0]:  ## 3.X is default if dual system
    import tkinter as tk     ## Python 3.x
else:
    import Tkinter as tk     ## Python 2.x

class StoreAVariable():
    def __init__(self, root):
        self.root=root
        self.ex1 = tk.StringVar(root)
        self.ex1.set("Pick Option")
        option = tk.OptionMenu(root, self.ex1, "one", "two", "three")
        option.pack()

        tk.Button(self.root, text="Please choose", command=self.choice).pack()

    def choice(self):
        self.chosen = self.ex1.get()

        ## the rest has nothing to do with storing a value
        print('chosen {}'.format(self.chosen))
        self.ex1.set(self.chosen)
        self.root.quit()
        # return chosen


root = tk.Tk()
RV=StoreAVariable(root)
root.mainloop()

print('-'*50)
print('After tkinter exits')
print('The final chosen value={}'.format(RV.chosen))