我已将原始编码更改为下面列出的内容：
module comparator (
input wire [7:0] A,
input wire [7:0] B,
input wire [7:0] C,
output reg [7:0] D,
output reg [7:0] E,
output reg [7:0] F
);
always @(*) begin
if (A>B && B>C) begin
D <= A;
E <= B;
F <= C;
end
else if (A>C && C>B) begin
D <= A;
E <= C;
F <= B;
end
else if (B>C && C>A) begin
D <= B;
E <= C;
F <= A;
end
else if (B>A && A>C) begin
D <= B;
E <= A;
F <= C;
end
else if (C>A && A>B) begin
D <= C;
E <= A;
F <= B;
end
else begin
D <= C;
E <= B;
F <= A;
end
end
endmodule
这是新的测试平台：
module testcomp;
reg [7:0] A, B, C;
wire [7:0] D, E, F;
comparator uut (
.A(A),
.B(B),
.C(C),
.D(D),
.E(E),
.F(F)
);
initial begin
A = 0;
repeat (3) begin
B = 0;
repeat (3) begin
C = 0;
repeat (3) begin
#10;
$display ("TESTING A=%d, B=%d, and C=%d yields D=%d, E=%d, F=%d", A, B, C, D, E, F);
if (A>B && B>C && D!=A && E!=B && F!=C) begin
$display ("ERROR!");
$finish;
end
if (A>C && C>B && D!=A && E!=C && F!=B) begin
$display ("ERROR!");
$finish;
end
if (B>A && A>C && D!=B && E!=A && F!=C) begin
$display ("ERROR!");
$finish;
end
if (B>C && C>A && D!=B && E!=C && F!=A) begin
$display ("ERROR!");
$finish;
end
if (C>A && A>B && D!=C && E!=A && F!=B) begin
$display ("ERROR!");
$finish;
end
if (C>B && B>A && D!=C && E!=B && F!=A) begin
$display ("ERROR!");
$finish;
end
C = C + 1;
end
B = B + 1;
end
A = A + 1;
end
$display ("PASSED!");
$finish;
end
endmodule
新帖子： 这解决了我通过更改为（A＆gt; B＆amp; B＆gt; C）来比较值的问题，但是当我查看结果时，我仍然有一些问题。结果如下：
[2016-12-11 14:05:13 EST] iverilog '-Wall' design.sv testbench.sv && unbuffer vvp a.out
TESTING A= 0, B= 0, and C= 0 yields D= 0, E= 0, F= 0
TESTING A= 0, B= 0, and C= 1 yields D= 1, E= 0, F= 0
TESTING A= 0, B= 0, and C= 2 yields D= 2, E= 0, F= 0
**TESTING A= 0, B= 1, and C= 0 yields D= 0, E= 1, F= 0**
TESTING A= 0, B= 1, and C= 1 yields D= 1, E= 1, F= 0
TESTING A= 0, B= 1, and C= 2 yields D= 2, E= 1, F= 0
**TESTING A= 0, B= 2, and C= 0 yields D= 0, E= 2, F= 0**
TESTING A= 0, B= 2, and C= 1 yields D= 2, E= 1, F= 0
TESTING A= 0, B= 2, and C= 2 yields D= 2, E= 2, F= 0
**TESTING A= 1, B= 0, and C= 0 yields D= 0, E= 0, F= 1**
**TESTING A= 1, B= 0, and C= 1 yields D= 1, E= 0, F= 1**
TESTING A= 1, B= 0, and C= 2 yields D= 2, E= 1, F= 0
**TESTING A= 1, B= 1, and C= 0 yields D= 0, E= 1, F= 1**
TESTING A= 1, B= 1, and C= 1 yields D= 1, E= 1, F= 1
TESTING A= 1, B= 1, and C= 2 yields D= 2, E= 1, F= 1
TESTING A= 1, B= 2, and C= 0 yields D= 2, E= 1, F= 0
**TESTING A= 1, B= 2, and C= 1 yields D= 1, E= 2, F= 1**
TESTING A= 1, B= 2, and C= 2 yields D= 2, E= 2, F= 1
**TESTING A= 2, B= 0, and C= 0 yields D= 0, E= 0, F= 2**
TESTING A= 2, B= 0, and C= 1 yields D= 2, E= 1, F= 0
**TESTING A= 2, B= 0, and C= 2 yields D= 2, E= 0, F= 2**
TESTING A= 2, B= 1, and C= 0 yields D= 2, E= 1, F= 0
**TESTING A= 2, B= 1, and C= 1 yields D= 1, E= 1, F= 2**
**TESTING A= 2, B= 1, and C= 2 yields D= 2, E= 1, F= 2**
**TESTING A= 2, B= 2, and C= 0 yields D= 0, E= 2, F= 2**
**TESTING A= 2, B= 2, and C= 1 yields D= 1, E= 2, F= 2**
TESTING A= 2, B= 2, and C= 2 yields D= 2, E= 2, F= 2
PASSED!
Done
正如您所标记/加星标的人所看到的那样，仍然存在问题，而不是正确地比较这些值。它是我的代码中的东西还是我错过了一个不允许它正常运行的约束？
原件：
主要问题是我一直陷入设计代码的主要代码的else分支（当我使用（A＆gt; B＆gt; C）来比较代码中的值时）。我猜这些数字在主代码中根本没有比较，问题在于我如何尝试比较这些值。能帮我找到一种方法来正确比较三个8位输入，以避免卡在else分支中吗？非常感谢提前。
答案 0 :(得分：0)
我终于解决了这个问题。我需要小心价值可能相同的时候。因此，我结束了以下代码：
module comparator (
input clock,
input wire [7:0] A,
input wire [7:0] B,
input wire [7:0] C,
output reg [7:0] D,
output reg [7:0] E,
output reg [7:0] F
);
always @(*) begin
if (A>=B && B>=C) begin
D <= A;
E <= B;
F <= C;
end
else if (A>=C && C>=B) begin
D <= A;
E <= C;
F <= B;
end
else if (B>=C && C>=A) begin
D <= B;
E <= C;
F <= A;
end
else if (B>=A && A>=C) begin
D <= B;
E <= A;
F <= C;
end
else if (C>=A && A>=B) begin
D <= C;
E <= A;
F <= B;
end
else begin
D <= C;
E <= B;
F <= A;
end
end
endmodule
测试平台：
module testcomp;
input clock;
reg [7:0] A, B, C;
wire [7:0] D, E, F;
comparator uut (
.clock(clock),
.A(A),
.B(B),
.C(C),
.D(D),
.E(E),
.F(F)
);
initial begin
A = 0;
repeat (255) begin
B = 0;
repeat (255) begin
C = 0;
repeat (255) begin
#10;
$display ("TESTING A=%h, B=%h, and C=%h yields D=%h, E=%h, F=%h", A, B, C, D, E, F);
if (A>B && B>C && D!=A && E!=B && F!=C) begin
$display ("ERROR!");
$finish;
end
if (A>C && C>B && D!=A && E!=C && F!=B) begin
$display ("ERROR!");
$finish;
end
if (B>A && A>C && D!=B && E!=A && F!=C) begin
$display ("ERROR!");
$finish;
end
if (B>C && C>A && D!=B && E!=C && F!=A) begin
$display ("ERROR!");
$finish;
end
if (C>A && A>B && D!=C && E!=A && F!=B) begin
$display ("ERROR!");
$finish;
end
if (C>B && B>A && D!=C && E!=B && F!=A) begin
$display ("ERROR!");
$finish;
end
C = C + 1;
end
B = B + 1;
end
A = A + 1;
end
$display ("PASSED!");
$finish;
end
endmodule
通过以下提取（从中间拉出）结果：
[2016-12-12 08:56:45 EST] iverilog '-Wall' design.sv testbench.sv && unbuffer vvp a.out
TESTING A=00, B=0c, and C=05 yields D=0c, E=05, F=00
TESTING A=00, B=0c, and C=06 yields D=0c, E=06, F=00
TESTING A=00, B=0c, and C=07 yields D=0c, E=07, F=00
TESTING A=00, B=0c, and C=08 yields D=0c, E=08, F=00
TESTING A=00, B=0c, and C=09 yields D=0c, E=09, F=00
TESTING A=00, B=0c, and C=0a yields D=0c, E=0a, F=00
TESTING A=00, B=0c, and C=0b yields D=0c, E=0b, F=00
TESTING A=00, B=0c, and C=0c yields D=0c, E=0c, F=00
TESTING A=00, B=0c, and C=0d yields D=0d, E=0c, F=00
TESTING A=00, B=0c, and C=0e yields D=0e, E=0c, F=00
TESTING A=00, B=0d, and C=09 yields D=0d, E=09, F=00
TESTING A=00, B=0d, and C=0a yields D=0d, E=0a, F=00
TESTING A=00, B=0d, and C=0b yields D=0d, E=0b, F=00
TESTING A=00, B=0d, and C=0c yields D=0d, E=0c, F=00
TESTING A=00, B=0d, and C=0d yields D=0d, E=0d, F=00
TESTING A=00, B=0d, and C=0e yields D=0e, E=0d, F=00
TESTING A=00, B=0d, and C=0f yields D=0f, E=0d, F=00
TESTING A=00, B=0d, and C=fd yields D=fd, E=0d, F=00
TESTING A=00, B=0d, and C=fe yields D=fe, E=0d, F=00
TESTING A=00, B=0e, and C=00 yields D=0e, E=00, F=00
TESTING A=00, B=0e, and C=01 yields D=0e, E=01, F=00
TESTING A=00, B=0e, and C=02 yields D=0e, E=02, F=00
TESTING A=00, B=0e, and C=03 yields D=0e, E=03, F=00
TESTING A=00, B=0e, and C=04 yields D=0e, E=04, F=00
TESTING A=00, B=0e, and C=05 yields D=0e, E=05, F=00
TESTING A=00, B=0e, and C=06 yields D=0e, E=06, F=00
TESTING A=00, B=0e, and C=07 yields D=0e, E=07, F=00
TESTING A=00, B=0e, and C=08 yields D=0e, E=08, F=00
TESTING A=00, B=0e, and C=09 yields D=0e, E=09, F=00
TESTING A=00, B=0e, and C=0a yields D=0e, E=0a, F=00
TESTING A=00, B=0e, and C=0b yields D=0e, E=0b, F=00
TESTING A=00, B=0e, and C=0c yields D=0e, E=0c, F=00
TESTING A=00, B=0e, and C=0d yields D=0e, E=0d, F=00
TESTING A=00, B=0e, and C=0e yields D=0e, E=0e, F=00
TESTING A=00, B=0e, and C=0f yields D=0f, E=0e, F=00
TESTING A=00, B=0e, and C=10 yields D=10, E=0e, F=00
TESTING A=00, B=0e, and C=11 yields D=11, E=0e, F=00
TESTING A=00, B=0f, and C=fd yields D=fd, E=0f, F=00
TESTING A=00, B=0f, and C=fe yields D=fe, E=0f, F=00
TESTING A=00, B=10, and C=00 yields D=10, E=00, F=00
TESTING A=00, B=10, and C=01 yields D=10, E=01, F=00
TESTING A=00, B=10, and C=02 yields D=10, E=02, F=00
TESTING A=00, B=10, and C=03 yields D=10, E=03, F=00
TESTING A=00, B=10, and C=04 yields D=10, E=04, F=00
TESTING A=00, B=10, and C=05 yields D=10, E=05, F=00
TESTING A=00, B=10, and C=06 yields D=10, E=06, F=00
TESTING A=00, B=10, and C=07 yields D=10, E=07, F=00
TESTING A=00, B=10, and C=08 yields D=10, E=08, F=00
TESTING A=00, B=10, and C=09 yields D=10, E=09, F=00
TESTING A=00, B=10, and C=0a yields D=10, E=0a, F=00
TESTING A=00, B=10, and C=0b yields D=10, E=0b, F=00
TESTING A=00, B=10, and C=0c yields D=10, E=0c, F=00
TESTING A=00, B=10, and C=0d yields D=10, E=0d, F=00
TESTING A=00, B=10, and C=0e yields D=10, E=0e, F=00
TESTING A=00, B=10, and C=0f yields D=10, E=0f, F=00
TESTING A=00, B=10, and C=10 yields D=10, E=10, F=00
TESTING A=00, B=10, and C=11 yields D=11, E=10, F=00
TESTING A=00, B=10, and C=12 yields D=12, E=10, F=00
TESTING A=00, B=10, and C=13 yields D=13, E=10, F=00
TESTING A=00, B=10, and C=fd yields D=fd, E=10, F=00
TESTING A=00, B=10, and C=fe yields D=fe, E=10, F=00
TESTING A=00, B=11, and C=00 yields D=11, E=00, F=00
TESTING A=00, B=11, and C=01 yields D=11, E=01, F=00
TESTING A=00, B=11, and C=02 yields D=11, E=02, F=00
TESTING A=00, B=11, and C=03 yields D=11, E=03, F=00
TESTING A=00, B=11, and C=04 yields D=11, E=04, F=00
TESTING A=00, B=11, and C=05 yields D=11, E=05, F=00
TESTING A=00, B=11, and C=06 yields D=11, E=06, F=00
TESTING A=00, B=11, and C=07 yields D=11, E=07, F=00
TESTING A=00, B=11, and C=08 yields D=11, E=08, F=00
TESTING A=00, B=11, and C=09 yields D=11, E=09, F=00
TESTING A=00, B=11, and C=0a yields D=11, E=0a, F=00
TESTING A=00, B=11, and C=0b yields D=11, E=0b, F=00
TESTING A=00, B=11, and C=0c yields D=11, E=0c, F=00
TESTING A=00, B=11, and C=0d yields D=11, E=0d, F=00
TESTING A=00, B=11, and C=0e yields D=11, E=0e, F=00
TESTING A=00, B=11, and C=0f yields D=11, E=0f, F=00
TESTING A=00, B=11, and C=10 yields D=11, E=10, F=00
TESTING A=00, B=11, and C=11 yields D=11, E=11, F=00
TESTING A=00, B=11, and C=12 yields D=12, E=11, F=00
TESTING A=00, B=11, and C=13 yields D=13, E=11, F=00
TESTING A=00, B=11, and C=14 yields D=14, E=11, F=00
TESTING A=00, B=11, and C=15 yields D=15, E=11, F=00
TESTING A=00, B=11, and C=16 yields D=16, E=11, F=00
TESTING A=00, B=11, and C=17 yields D=17, E=11, F=00
TESTING A=00, B=11, and C=fd yields D=fd, E=11, F=00
TESTING A=00, B=11, and C=fe yields D=fe, E=11, F=00
TESTING A=00, B=12, and C=00 yields D=12, E=00, F=00
TESTING A=00, B=12, and C=01 yields D=12, E=01, F=00
TESTING A=00, B=12, and C=02 yields D=12, E=02, F=00
TESTING A=00, B=12, and C=03 yields D=12, E=03, F=00
TESTING A=00, B=12, and C=04 yields D=12, E=04, F=00
TESTING A=00, B=12, and C=05 yields D=12, E=05, F=00
TESTING A=00, B=12, and C=06 yields D=12, E=06, F=00
TESTING A=00, B=12, and C=07 yields D=12, E=07, F=00
TESTING A=00, B=12, and C=08 yields D=12, E=08, F=00
TESTING A=00, B=12, and C=09 yields D=12, E=09, F=00
TESTING A=00, B=12, and C=0a yields D=12, E=0a, F=00
TESTING A=00, B=12, and C=0b yields D=12, E=0b, F=00
TESTING A=00, B=12, and C=0c yields D=12, E=0c, F=00
TESTING A=00, B=12, and C=0d yields D=12, E=0d, F=00
TESTING A=00, B=12, and C=0e yields D=12, E=0e, F=00
TESTING A=00, B=12, and C=0f yields D=12, E=0f, F=00
TESTING A=00, B=12, and C=10 yields D=12, E=10, F=00
TESTING A=00, B=12, and C=11 yields D=12, E=11, F=00
TESTING A=00, B=12, and C=12 yields D=12, E=12, F=00
TESTING A=00, B=12, and C=13 yields D=13, E=12, F=00
TESTING A=00, B=12, and C=14 yields D=14, E=12, F=00
TESTING A=00, B=12, and C=15 yields D=15, E=12, F=00
TESTING A=00, B=12, and C=16 yields D=16, E=12, F=00
TESTING A=00, B=12, and C=17 yields D=17, E=12, F=00
TESTING A=00, B=12, and C=fd yields D=fd, E=12, F=00
TESTING A=00, B=12, and C=fe yields D=fe, E=12, F=00
TESTING A=00, B=13, and C=00 yields D=13, E=00, F=00
TESTING A=00, B=13, and C=01 yields D=13, E=01, F=00
TESTING A=00, B=13, and C=02 yields D=13, E=02, F=00
TESTING A=00, B=13, and C=03 yields D=13, E=03, F=00
TESTING A=00, B=13, and C=04 yields D=13, E=04, F=00
TESTING A=00, B=13, and C=05 yields D=13, E=05, F=00
TESTING A=00, B=13, and C=06 yields D=13, E=06, F=00
TESTING A=00, B=13, and C=07 yields D=13, E=07, F=00
TESTING A=00, B=13, and C=08 yields D=13, E=08, F=00
TESTING A=00, B=13, and C=09 yields D=13, E=09, F=00
TESTING A=00, B=13, and C=0a yields D=13, E=0a, F=00
TESTING A=00, B=13, and C=0b yields D=13, E=0b, F=00
TESTING A=00, B=13, and C=0c yields D=13, E=0c, F=00
TESTING A=00, B=13, and C=0d yields D=13, E=0d, F=00
TESTING A=00, B=13, and C=0e yields D=13, E=0e, F=00
TESTING A=00, B=13, and C=0f yields D=13, E=0f, F=00
TESTING A=00, B=13, and C=10 yields D=13, E=10, F=00
TESTING A=00, B=13, and C=11 yields D=13, E=11, F=00
TESTING A=00, B=13, and C=12 yields D=13, E=12, F=00
TESTING A=00, B=13, and C=13 yields D=13, E=13, F=00
TESTING A=00, B=13, and C=14 yields D=14, E=13, F=00
TESTING A=00, B=13, and C=15 yields D=15, E=13, F=00
TESTING A=00, B=13, and C=16 yields D=16, E=13, F=00
TESTING A=00, B=13, and C=17 yields D=17, E=13, F=00
Done