Question

我想在xilinix的verilog中制作一个参数化FIR滤波器。这是我的代码：

module FIRFilter(xInput, clock, reset, filterCoeff, yOutput);
parameter inputBits = 8, lengthOfFilter = 4, coeffBitLength = 8, lengthOfCoeff = lengthOfFilter + 1, outputBitWdth = 2 * inputBits;
input [(coeffBitLength * lengthOfCoeff) - 1 : 0] filterCoeff;
input clock, reset;
input [inputBits - 1 : 0] xInput;
reg [outputBitWdth - 1 : 0] addWires [lengthOfFilter - 1 : 0];
output reg [outputBitWdth - 1 : 0] yOutput;
reg [inputBits - 1 : 0] registers [lengthOfFilter - 1 : 0];
integer i, j;
always @ (posedge clock, posedge reset)
begin
    if(reset)
    begin
        for(i = 0; i < lengthOfFilter; i = i + 1)
        begin
            registers[i] <= 0;
        end
    end
    else
    begin
        registers[0] <= xInput;
        for(i = 1; i < lengthOfFilter; i = i + 1)
        begin
            registers[i] <= registers[i - 1];
        end
    end
end
always @ (posedge clock)
begin
    addWires[0] = filterCoeff[(lengthOfFilter * coeffBitLength) - 1 : (lengthOfFilter - 1) * coeffBitLength] * xInput;
    for(j = 1; j < lengthOfFilter; j = j + 1)
    begin
        addWires[j] = (filterCoeff[((j + 1) * coeffBitLength) - 1 : j * coeffBitLength] * registers[j - 1]) + addWires[j - 1];
    end
    yOutput = (filterCoeff[coeffBitLength - 1 : 0] * registers[lengthOfFilter - 1]) + addWires[lengthOfFilter - 1];
end
endmodule

但我一直收到此错误

ERROR:HDLCompilers:109 - "FIRFilter.v" line 33 Most significant bit operand in part-select of vector wire 'filterCoeff' is illegal
ERROR:HDLCompilers:110 - "FIRFilter.v" line 33 Least significant bit operand in part-select of vector wire 'filterCoeff' is illegal
ERROR:HDLCompilers:45 - "FIRFilter.v" line 33 Illegal right hand side of blocking assignment

我在线搜索了解决方案，但没有任何满意的答案。有人可以帮我吗？

Answer 1

Verilog不允许部分选择signal[msb:lsb]，其中msb和lsb不是常数。您可以使用另一种称为索引部分选择的结构，在该结构中您可以指定恒定宽度，但偏移量为signal[offset+:width]

addWires[0] = filterCoeff[(lengthOfFilter * coeffBitLength) +:coeffBitLength] * xInput;

矢量线部分选择中的最高有效位操作数是非法的

1 个答案: