Question

所以我试图在verilog中设计一个4位进位选择加法器，并使用以下代码进行设计：

module fullAdder (S,Cout,P,G,A,B,Cin);
// Define all inputs and outputs for single bit Fulll Adder
    output S;
    output Cout;
    output P;
    output G;
    input A;
    input B;
    input Cin;

// Full Adder body, define structure and internal wiring
    wire t1, t2, t3;

    xor xor1 (t1, A, B);
    xor xor2 (S, t1, Cin);

    or or1 (P, A, B);
    and and1 (G, A, B);
    and and2 (t2, P, Cin);
    or or2 (Cout, t2, G);

endmodule 

module carrySelect (sum, cout, a, b, cin);
  output [3:0] sum;    //sum output of the adder, 4 bits wide
  output cout;           //carry out of the adder
  input [3:0] a;          //input a, 4 bits wide
  input [3:0] b;         //input b, 4 bits wide
  input cin;              //carry in of the adder

  reg ch, cl;   //temporary variables to define cases that previous carry is high or low
  wire [3:0] C;     //carry bus
  wire [3:0] P,G;   //buses for P and G outputs of fullAdder
  wire [1:0] s0, s1, s2, s3;    //temporary buses for cases of sums
  wire [1:0] c0, c1, c2, c3;    //temporary buses for cases of carries

  assign ch = 1;    //assign ch to high and cl to low
  assign cl = 0;

  //least significant full adder computation
  fullAdder f0_h (s0[0],c0[0],p0[0], g0[0], a[0], b[0], ch); 
  fullAdder f0_l (s0[1],c0[1],p0[1], g0[1], a[0], b[0], cl);

  fullAdder f1_h (s1[0],c1[0],p1[0], g1[0], a[0], b[0], ch);
  fullAdder f1_l(s1[1],c1[1],p1[1], g1[1], a[0], b[0], cl);

  fullAdder f2_h (s2[0],c2[0],p2[0], g2[0], a[0], b[0], ch);
  fullAdder f2_l (s2[1],c2[1],p2[1], g2[1], a[0], b[0], cl);

  //most significant full adder computation
  fullAdder f3_h (s3[0],c3[0],p3[0], g3[0], a[0], b[0], ch);
  fullAdder f3_l (s3[1],c3[1],p3[1], g3[1], a[0], b[0], cl);

  //select output depending on values of carries

  if (cin == 1) begin
    assign sum[0] = s0[0];
    assign C[0] = c0[0];
  end else begin
    assign sum[0] = s0[1];  
    assign C[0] = c0[1];
  end

  if(C[0] == 1) begin
    assign sum[1] = s1[0];
    assign C[1] = c1[0];
  end else begin
    assign sum[1] = s1[1];  
    assign C[1] = c1[1];
  end

  if(C[1]) begin
    assign sum[2] = s2[0];
    assign C[2] = c2[0];
  end else begin
    assign sum[2] = s2[1];  
    assign C[2] = c2[1];
  end

  if(C[2]) begin
    assign sum[3] = s3[0];
    assign C[3] = c3[0];
  end else begin
    assign sum[3] = s3[1];  
    assign C[3] = c3[1];
  end

  //assign carry out
  assign cout = C[3];

endmodule

全加器功能完全正常，所以没有问题。当我尝试编译代码时，我从if语句中得到错误，并获得有关隐式定义的警告以及无法在ifs中评估条件的genvar的错误。我对verilog相当新，所以如果这是一个微不足道的修复我道歉。任何帮助表示赞赏。

EDIT1：抛出错误/警告消息

design.sv:57: warning: implicit definition of wire fullAdderTest.UUT.cin.
design.sv:57: error: Cannot evaluate genvar conditional expression: (cin)==('sd1)
design.sv:57: error: Cannot evaluate genvar conditional expression: (cin)==('sd1)
design.sv:65: warning: implicit definition of wire fullAdderTest.UUT.C.
design.sv:65: error: Cannot evaluate genvar conditional expression: (C['sd0])==('sd1)
design.sv:65: error: Cannot evaluate genvar conditional expression: (C['sd0])==('sd1)
design.sv:73: warning: Constant bit select [1] is after vector C[0:0].
design.sv:73:        : Replacing select with a constant 1'bx.
design.sv:73: warning: Constant bit select [1] is after vector C[0:0].
design.sv:73:        : Replacing select with a constant 1'bx.
design.sv:81: warning: Constant bit select [2] is after vector C[0:0].
design.sv:81:        : Replacing select with a constant 1'bx.
design.sv:81: warning: Constant bit select [2] is after vector C[0:0].
design.sv:81:        : Replacing select with a constant 1'bx.
4 error(s) during elaboration.

Answer 1

if或always块之外的initial语句被视为if generate块内的语句。生成的if语句将接受文字常量（硬编码值），参数和genvars。它不接受网络或寄存器类型（即：wire，reg，integer等）。生成块在精化过程中进行评估，因此不能依赖于具有动态值的模拟变量。

您希望根据输入值有条件地选择sum和C的值。有几个选项可以做到这一点：

一种选择是制作内联条件声明：

assign sum[0] = cin ? s0[0] : s0[1];
assign C[0]   = cin ? c0[0] : c0[1];
// ...

或者您可以选择索引（效果相同）：

assign sum[0] = s0[!cin];
assign C[0]   = c0[!cin];
assign sum[1] = s1[!C[0]];
assign C[1]   = c1[!C[0]];
// ...

或者制作sum和C reg类型，并将所有if语句放在always块中（删除assign s）：

always @* begin
  if (cin == 1) begin
    sum[0] = s0[0];
    C[0] = c0[0];
  end
  else begin
    sum[0] = s0[1];  
    C[0] = c0[1];
  end
  // ...
end

Verilog 4位进位选择加法器

1 个答案: