Question

您好我问了一个关于我的项目的问题here我已经做了相当多的工作并取得了以下进展：

module project1 where

open import Data.Empty

open import Data.Unit hiding (_≟_)
open import Data.Nat hiding (_≟_; _⊔_)
open import Data.String
open import Data.List
open import Data.Vec hiding (_∈_)

open import Data.Sum
open import Data.Product
open import Function
open import Relation.Nullary
open import Relation.Binary

open import Relation.Binary.PropositionalEquality

open import Data.Vec hiding (_∈_)

data Bool : Set where
  true  : Bool
  false : Bool

-- The definition of a circuit and series and parallel combination of the circuit
data Ckt   :  Set where
  bool     : Bool → Ckt
  gate     : ℕ → ℕ → Ckt
  series   : Ckt → Ckt → Ckt
  parallel : Ckt → Ckt → Ckt


And : Ckt
And = gate 2 1

Not :  Ckt
Not = gate 1 1

Or : Ckt
Or = gate 2 1

Nand : Ckt
Nand = gate 2 1

Nand₁ : Ckt
Nand₁ = series And Not 


--Static Semantics


data Ctxt : Set where
  □   : Ctxt


data _⊢_  : (Γ : Ctxt) → (e : Ckt)  → Set where

  BoolT     : ∀ {Γ b} → Γ ⊢ bool b 
  GateT     : ∀ {Γ i o} →  Γ ⊢ gate  i o
  SeriesT   : ∀ {Γ c₁ c₂} →  Γ ⊢ c₁ → Γ ⊢ c₂  → Γ ⊢ series  c₁ c₂ 
  ParallelT : ∀ {Γ c₁ c₂} →  Γ ⊢ c₁ → Γ ⊢ c₂  → Γ ⊢ parallel  c₁ c₂

--dynamic semantics

--The type of input and output from the dynamics
in/out =   List Bool 

--closure is made up if the ckt and input/output
ClosureL : Set
ClosureL =   Ckt × in/out  


data FrameL  : Set where
  SeriesLK   : ClosureL → FrameL
  ParallelLK : ClosureL → FrameL
  SeriesRK   : in/out → FrameL
  ParallelRk : in/out → FrameL

ContL : Set
ContL = List FrameL


data StateL : Set where
  Enter : ClosureL → ContL → StateL
  Return : ContL → in/out → StateL

stepL : StateL → StateL
stepL (Enter (bool b , ρ) κ) = Return κ {!!}
stepL (Enter (gate i o , ρ) κ) = Return κ {!!}
stepL (Enter (series c₁ c₂ , ρ) κ) = Enter (c₁ , ρ) (SeriesLK (c₂ , ρ) ∷  κ)
stepL (Enter (parallel c₁ c₂ , ρ) κ) =  Enter (c₁ , ρ) (ParallelLK (c₂ , ρ) ∷  κ)

stepL (Return [] output) = Return [] output

stepL (Return (SeriesLK (e₂ , ρ) ∷ κ) output) = Enter (e₂ , {!!}) {!!} 

stepL (Return (ParallelLK (e₂ , ρ) ∷ κ) output) =  Enter (e₂ , {!!}) {!!} 

stepL (Return (SeriesRK x  ∷ κ) output) = {!!}
stepL (Return (ParallelRk x ∷ κ) output) = {!!}

我的问题在于动态语义。我如何确保CEK机器的输入（修改后的cek cuz其ckt输入和堆栈而不是ckt env和堆栈）和输出的长度与电路指定的长度相同。我简短地说明如何在将输入/输出列表作为输入提供给机器时指定它的长度？请随时指出您在我的代码中看到的任何其他问题。

关于AGDA第二部分中非常浅嵌入VHDL的指南

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