无效的模块实例化systemverilog

时间:2016-12-22 07:49:32

标签: verilog system-verilog hdl

我正在尝试在eda playground中运行此代码,但我收到以下错误:

module array_redu(); 
  byte b[] = { 1, 2, 3, 4 }; 
  int sum,product,b_xor;
  initial
    begin 
      sum =b.sum ;  // y becomes 10 => 1 + 2 + 3 + 4
      product =b.product ;  // y becomes 24 => 1 * 2 * 3 * 4
      b_xor=b.xor with (item+ 4 );  // y becomes 12 => 5 ^ 6 ^ 7 ^8 
      $display(" Sum is %0d, product is %0d, xor is  %0b",sum,product,b_xor)
      end
endmodule

我收到以下错误:

design.sv:2: syntax error
design.sv:2: error: Invalid module instantiation
design.sv:3: syntax error
design.sv:3: error: Invalid module instantiation
design.sv:8: syntax error
design.sv:8: error: malformed statement
design.sv:10: syntax error

1 个答案:

答案 0 :(得分:1)

我在EDA Playground上使用Aldec Riviera Pro模拟了您的代码。只有一个错误:您在$display行的末尾错过了一个分号。