Question

我正在尝试实现通用（可参数化）矩阵加法器。

到目前为止，我只有两个3x3矩阵的矩阵加法器。这是matrix_add：

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.std_logic_UNSIGNED.all;
USE ieee.numeric_std.all;

LIBRARY work;
USE work.matrix_pack.all;

ENTITY matrix_add  is
  PORT (
    t_clk_i          : IN    STD_LOGIC;  -- System Clock (66.6667 MHz) (
    s_rst_l_i        : IN    STD_LOGIC;  -- Reset input
    d_mat1_i         : IN    matrix_t; -- Matrix 1 
    d_mat2_i         : IN    matrix_t; -- Matrix 2 
    d_result_o       : OUT   matrix_t  -- Addition Result  
  );
END matrix_add;

ARCHITECTURE rtl_matrix_add OF matrix_add IS

BEGIN
  p_add : PROCESS(t_clk_i, s_rst_l_i)
  BEGIN
    IF s_rst_l_i = '0' THEN
      d_result_o <= (OTHERS => (OTHERS => (OTHERS => '1')));
    ELSIF RISING_EDGE(t_clk_i) THEN
      FOR i IN 0 TO (d_mat1_i'LENGTH(1)-1) LOOP
        FOR j IN 0 TO (d_mat1_i'LENGTH(2)-1) LOOP
          d_result_o(i, j) <= d_mat1_i(i, j) + d_mat2_i(i, j);
        END LOOP;
      END LOOP;
    END IF;
  END PROCESS p_add;

END rtl_matrix_add;

这是包裹：

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.std_logic_UNSIGNED.all;
USE ieee.numeric_std.all;

PACKAGE matrix_pack IS
  TYPE matrix_t is ARRAY (0 TO 2, 0 TO 2) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
END matrix_pack;

如何使矩阵的大小通用？不幸的是我必须使用一个包，因为Quartus不接受 ARRAY（0到2,0到2）OF STD_LOGIC_VECTOR（7 DOWNTO 0）作为信号输入类型，否则我不需要包和我的问题会解决。

我听说过这可以在VHDL 2008中完成，但是怎么样，Quartus或Modelsim会接受这个吗？

由于

Answer 1

谢谢fpga_magik的回答。有效。代码结果如下：

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.std_logic_UNSIGNED.all;
USE ieee.numeric_std.all;

LIBRARY work;
USE work.matrix_pack.all;

ENTITY matrix_add is
  GENERIC (
    M : INTEGER := 3;
    N : INTEGER := 2
    );
  PORT (
    t_clk_i          : IN    STD_LOGIC;                    -- System Clock (66.6667 MHz) (
    s_rst_l_i        : IN    STD_LOGIC;                    -- Reset input
    d_mat1_i         : IN    matrix_t(0 TO M-1, 0 TO N-1); -- Matrix 1 
    d_mat2_i         : IN    matrix_t(0 TO M-1, 0 TO N-1); -- Matrix 2 
    d_result_o       : OUT   matrix_t(0 TO M-1, 0 TO N-1)  -- Addition Result  
  );
END matrix_add;

ARCHITECTURE rtl_matrix_add OF matrix_add IS

BEGIN
  p_add : PROCESS(t_clk_i, s_rst_l_i)
  BEGIN
    IF s_rst_l_i = '0' THEN
      d_result_o <= (OTHERS => (OTHERS => (OTHERS => '1')));
    ELSIF RISING_EDGE(t_clk_i) THEN
      FOR i IN 0 TO (d_mat1_i'LENGTH(1)-1) LOOP
        FOR j IN 0 TO (d_mat1_i'LENGTH(2)-1) LOOP
          d_result_o(i, j) <= d_mat1_i(i, j) + d_mat2_i(i, j);
        END LOOP;
      END LOOP;
    END IF;
  END PROCESS p_add;

END rtl_matrix_add;

和包装如下：

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.std_logic_UNSIGNED.all;
USE ieee.numeric_std.all;

PACKAGE matrix_pack IS
  TYPE matrix_t is ARRAY (natural range <>, natural range <>) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
END matrix_pack;

非常感谢!! ：）

在VHDL中将泛型传递给包

1 个答案: