Question

我正在寻找正确的语法来使用泛型和进程中的循环来构建泛型行延迟包。我理解for循环与generate一起用于并发语句，但肯定必须有一种方法来构建它。

例如：

entity Delay_Line is
    Generic (
        CLK_DELAYS : integer := 10);
    Port ( 
        CLK    : in  STD_LOGIC;
        i_Din  : in  STD_LOGIC;
        o_Q    : out  STD_LOGIC;
        o_Qnot : out  STD_LOGIC);
    end Delay_Line;

architecture Delay_Line_arch of Delay_Line is

    signal din_dly : std_logic_vector(CLK_DELAYS-1 downto 0);
begin
    din_dly(0) <= i_Din;

    process(CLK)
    begin
        if rising_edge(CLK) then
            for index in 0 to CLK_DELAYS-1 generate
            begin
                din_dly(index+1) <= din_dly(index);
            end;
        end if;
    end process;
    o_Q        <= din_dly(CLK_DELAYS);
    o_Qnot     <= NOT (din_dly(CLK_DELAYS));

end Delay_Line_arch;

通常我会添加一堆：

din_delay(9) <= din_delay(8);
din_delay(8) <= din_delay(7);
...

在代码中，但说实话，我想要一些可以重复使用的东西。

Answer 1

使用这种精细的方法实现移位寄存器并不是必需的。您可以使用数组连接和切片直接在一行中实现它们。

constant DELAY_STAGES : positive := 10; -- Or use a generic parameter

signal delay_line : std_logic_vector(1 to DELAY_STAGES);
...

process(clk) is
begin
  if rising_edge(clk) then
    delay_line <= i_Din & delay_line(1 to DELAY_STAGES-1); -- Shift right
  end if;
end process;

-- Retrieve the end of the delay without a hard-coded index
o_Q <= delay_line(delay_line'high);

这种方法的简洁性几乎消除了使用端口和通用映射实例化组件所需的任何便利。此外，您可以灵活地利用您可能需要的任何中间信号。

Answer 2

好吧我还没有50个代表，但要让Pablo R的方法与大型公共汽车一起工作并延迟bus_size := 16和delay := 256。我不得不改变：

temp_bus2 <= i_bus2 & temp_bus2(delay*bus_size - 1 downto (delay-1)*bus_size);

到

temp_bus2 <= i_bus2 & temp_bus2(delay*bus_size - 1 downto (bus_size);

Answer 3

有点晚了，但这是我的generic_delay组件：

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY generic_delay is
  generic (
    bus_size    : natural;
    delay       : natural
    );
  port (
    i_Clock : IN  STD_LOGIC;
    i_reset : IN  STD_LOGIC;
    i_bus1  : in std_logic_vector(bus_size - 1 downto 0);
    i_bus2  : in std_logic_vector(bus_size - 1 downto 0);
    o_bus1  : out std_logic_vector(bus_size - 1 downto 0);
    o_bus2  : out std_logic_vector(bus_size - 1 downto 0)
    );
end generic_delay;


architecture a of generic_delay is

----------------------------
-- SIGNALS DECLARATION
----------------------------
  signal temp_bus1 : std_logic_vector(delay*bus_size - 1 downto 0);
  signal temp_bus2 : std_logic_vector(delay*bus_size - 1 downto 0);

BEGIN

-----------------------------------------
-- SYNCHRONOUS PROCESS
-----------------------------------------
  process(i_Clock, i_reset)

  begin

    if i_reset = '1' then
      temp_bus1 <= (others => '0');
      temp_bus2 <= (others => '0');

    elsif falling_edge(i_Clock) then
      if delay > 1 then
        temp_bus1 <= i_bus1 & temp_bus1(delay*bus_size - 1 downto (delay-1)*bus_size);
        temp_bus2 <= i_bus2 & temp_bus2(delay*bus_size - 1 downto (delay-1)*bus_size);
      else
        temp_bus1 <= i_bus1;
        temp_bus2 <= i_bus2;
      end if; 
    elsif (RISING_EDGE(i_Clock)) then

      o_bus1 <= temp_bus1(bus_size - 1 downto 0);
      o_bus2 <= temp_bus2(bus_size - 1 downto 0);      

    end if; -- reset + rising_edge(clk)

  end process logic;


-------------------------------------------------------

end a;

在VHDL中生成通用延迟包

3 个答案: