Question

我正在尝试在包内定义一个类型，其大小取决于组件泛型。这是我想要做的，但综合抱怨：

package DcoPack is
    component SinCosDco
    generic
    (
         g_LUT_DEPTH   : integer := 2**10;
         g_LUT_BIT_RES : integer := 15

    );
    port
    (
        reset       : in  std_logic;
        lClk        : in  std_logic;

        InFreqCtrl  : in  std_logic_vector(31 downto 0) := X"028F5C28";   
        InStartPhse : in  std_logic_vector(31 downto 0) := X"00000000";   

        OutDco      : out signed((g_LUT_BIT_RES - 1) downto 0)
    );


    type LutSinT is array(0 to g_LUT_DEPTH - 1) of 
            std_logic_vector(g_LUT_BIT_RES-1 downto 0);

    function f_QuantizationSgn(nbit : integer; max_abs : real; dval : real) 
    return std_logic_vector;

    function f_InitLutSin 
    return LutSinT;   
end package DcoPack;

package body DcoPack is
    function f_QuantizationSgn(nbit : integer; max_abs : real; dval : real) 
    return std_logic_vector is
        <function body>
    end function;

    function f_InitLutSin return LutSinT is
        <function body>
    end function;
end package body DcoPack;

和我的组件

library DCO_lib;
use DCO_lib.DcoPack.all;

entity Dco is
    generic
    (
         g_LUT_DEPTH   : integer := 2**10;
         g_LUT_BIT_RES : integer := 15
    );
    port
    (
        reset       : in  std_logic;
        lClk        : in  std_logic;

        InDcoEn     : in  std_logic;
        InFreqCtrl  : in  std_logic_vector(31 downto 0) := X"028F5C28";   
        InStartPhse : in  std_logic_vector(31 downto 0) := X"00000000";

        OutDco      : out signed((g_LUT_BIT_RES - 1) downto 0)
    );
end entity Dco;

architecture zDco of Dco is
    -- want to reference LutSinT in numerous components, it varies depending 
    -- on generics
    constant c_SinCosLut : LutSinT := f_InitLutSin;
... <rest of code is irrelevant

如上面的代码所示，我试图在每个组件中引用此类型。但是，我需要能够根据项目轻松改变通用参数，因此有没有办法让VHDL推断出正确的数组大小？或者我是否被锁定在包中定义g_LUT_DEPTH / g_LUT_BIT_RES或硬编码每个组件内的类型？

编辑：添加了澄清代码片段和解释。

Answer 1

是的，现在有。 VHDL-2008支持包装泛型。所以你可以写

library ieee;
use ieee.numeric_std.all;

entity SinCosDco is
    generic (
         g_LUT_DEPTH   : positive;
         g_LUT_BIT_RES : positive
         );
    port (
        OutDco      : out signed((g_LUT_BIT_RES - 1) downto 0)
        );
end entity;

architecture tmp of SinCosDco is
    use ieee.std_logic_1164.all;
begin
    OutDco <= to_signed(-1, g_LUT_BIT_RES);
end architecture;


library ieee;

package DcoPack is
    generic (
         g_LUT_DEPTH   : positive := 2**10;
         g_LUT_BIT_RES : positive := 15
         );
    use ieee.numeric_std.all;
    component SinCosDco
        generic (
             g_LUT_DEPTH   : positive := g_LUT_DEPTH;
             g_LUT_BIT_RES : positive := g_LUT_BIT_RES
             );
        port (
            OutDco      : out signed((g_LUT_BIT_RES - 1) downto 0)
            );
    end component;
    use ieee.std_logic_1164.all;
    type LutSinT is array(0 to g_LUT_DEPTH - 1) of std_logic_vector(g_LUT_BIT_RES-1 downto 0);

end package DcoPack;


entity e is end entity;

library ieee;

architecture a of e is
    constant g_LUT_DEPTH: positive := 2**7; -- remember integer is only 32 bits
    constant g_LUT_BIT_RES : positive := 8;

    package myDcoPack is new work.DcoPack
        generic map (
            g_LUT_DEPTH => g_LUT_DEPTH,
            g_LUT_BIT_RES => g_LUT_BIT_RES);
    -- use work.myDcoPack.all; -- optional

    use ieee.numeric_std.all;
    signal output : signed((g_LUT_BIT_RES - 1) downto 0);
    use ieee.std_logic_1164.all;
    signal lut : myDcoPack.LutSinT;
begin
    comp_inst : myDcoPack.SinCosDco
        port map ( OutDco => output );

    lut(0) <= std_logic_vector(output);
end architecture;

然而，2年前Vivado不支持此功能。不知道现在是否支持它。

在VHDL中引用实体泛型内部包？

1 个答案: