VHDL 2008＆gt;将正式的通用包传递给分层较低的包实例化

Question

正确编译和模拟以下两个包和实体，以便将d'19分配给信号test。

package genpkg is
  generic ( test: natural:=2 );
end package;

library mylib;
use mylib.genpkg;

package genotherpkg is
  generic ( package lgpkg is new mylib.genpkg generic map (<>);
            toadd: natural:=4 );
  constant myconst: natural range 0 to 63:=lgpkg.test+toadd;
end package;

library mylib;
use mylib.genpkg;
use mylib.genotherpkg;

entity ent is
end ent;

architecture arch of ent is
   package mygpkg is new mylib.genpkg generic map (3);
   package myogpkg is new mylib.genotherpkg generic map (mygpkg, 16);
   signal test: integer;
begin
   test <= myogpkg.myconst;
end arch;

但是，当我尝试使用中间包时：

library mylib;
use mylib.genpkg;
use mylib.genotherpkg;

package gentoppkg is
  generic ( package lpkg is new mylib.genpkg generic map (<>) );

  --package mylpkg is new mylib.genpkg generic map (lpkg.test);
  --package lopkg is new mylib.genotherpkg generic map ( mylpkg, 16 );
  package lopkg is new mylib.genotherpkg generic map ( lpkg, 16 );
end package;

library mylib;
use mylib.genpkg;
use mylib.gentoppkg;

entity otherent is
end otherent;

architecture arch of otherent is
   package mygpkg is new mylib.genpkg generic map (3);
   package mytgpkg is new mylib.gentoppkg generic map (mygpkg);
   signal test: integer;
begin
   test <= mytgpkg.lopkg.myconst; 
end arch;

模拟器崩溃，除非我用注释行替换lopkg中gentoppkg的实例化。但是，这需要将lpkg中的每个泛型映射到新实例mylpkg。难道我做错了什么？或者我应该与工具供应商合作？