Question

我想要选择菜单

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;


ENTITY aluall IS
PORT(
        A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        CLK:IN STD_LOGIC;
        LOAD: in std_logic;
        RESET: IN STD_LOGIC;
        D:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
        END aluall;

ARCHITECTURE structual OF aluall IS
SIGNAL finor,Rsub2,Rsub,Radd,Radd2,Radd1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rAnd : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal rePiso : std_logic;
SIGNAL fmulti : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL compare: STD_LOGIC_VECTOR(1 DOWNTO 0);
signal repo: std_logic_vector(7 downto 0);
signal choice: integer range 0 to 10;


COMPONENT orGate
PORT(    A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         F:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
        END COMPONENT;


COMPONENT   andGate
PORT(    A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         F:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
        END COMPONENT;

COMPONENT add1
PORT(
  A : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(7 downto 0));
END COMPONENT;

COMPONENT add2

port(
  B : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(7 downto 0));

END COMPONENT;



COMPONENT add

port(
  A : in std_logic_vector(7 downto 0);
  B : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(7 downto 0)); 
END COMPONENT;



BEGIN --i want make choice menu for what go to output
 process(A,B,choice)
 begin
 if(choice = 0) then
label0: andGate PORT MAP (A,B,rAnd);
else
label1: orGate PORT MAP (A,B,finor);
end if;
label2: add PORT MAP (A,B,Radd);
label3: sub PORT MAP (A,B,Rsub);
label4: sub2 PORT MAP (A,B,Rsub2);



end structual;

我有错误的非法顺序声明。

Answer 1

图书馆IEEE; 使用IEEE.STD_LOGIC_1164.ALL;

ENTITY aluall IS
PORT(
        A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        code : std_logic_vector(3 downto 0);
        CLK:IN STD_LOGIC;
        D:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
        END aluall;

ARCHITECTURE structual OF aluall IS
SIGNAL finor,Rsub2,Rsub,Radd,Radd2,Radd1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rAnd : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal rePiso : std_logic;
SIGNAL fmulti : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL compare: STD_LOGIC_VECTOR(7 DOWNTO 0);
signal repo: std_logic_vector(7 downto 0);


COMPONENT orGate
PORT(    A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         F:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
        END COMPONENT;


COMPONENT   andGate
PORT(    A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         F:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
        END COMPONENT;

COMPONENT add1
PORT(
  A : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(7 downto 0));
END COMPONENT;

COMPONENT add2

port(
  B : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(7 downto 0));

END COMPONENT;

COMPONENT multi
 port(
  A : in std_logic_vector(7 downto 0);
  B : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(15 downto 0));

END COMPONENT;

COMPONENT add

port(
  A : in std_logic_vector(7 downto 0);
  B : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(7 downto 0)); 
END COMPONENT;

COMPONENT sub
port(
  A : in std_logic_vector(7 downto 0);
  B : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(7 downto 0));  

END COMPONENT;

COMPONENT sub2

port(
  A : in std_logic_vector(7 downto 0);
  B : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(7 downto 0)); 

 END COMPONENT;

COMPONENT comparing
port(
  A : in std_logic_vector(7 downto 0);
  B : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(7 downto 0)
 );
END COMPONENT;

COMPONENT piso
port(
CLK,LOAD : in std_logic;
PI : in std_logic_vector(7 downto 0);
SO : out std_logic
);
END COMPONENT;


COMPONENT pipo

port(
clk:in std_logic;
pi: in std_logic_vector(7 downto 0);
po:out std_logic_vector(7 downto 0)

);
end COMPONENT;



begin
label0: andGate PORT MAP (A,B,rAnd);
label1: orGate PORT MAP (A,B,finor);
label2: add PORT MAP (A,B,Radd);
label3: sub PORT MAP (A,B,Rsub);
label4: sub2 PORT MAP (A,B,Rsub2);
label5: add1 PORT MAP (A,Radd1);
label6: add2 PORT MAP (B,Radd2);
label7: multi PORT MAP (A,B,fmulti);
label8: comparing PORT MAP (A,B,compare);
process(A,B,CLK,code)
begin




if (code = "0000") then
D<= rAnd;
elsif(code ="0001") then
D<= finor;
elsif(code ="0010") then
D<=Rsub;
elsif(code = "0011") then
D<=Radd;
elsif(code = "0100") then
D<=Rsub;
elsif(code = "0101") then
D<=Rsub2;
elsif(code = "0110") then
D<=Radd1;
elsif(code = "0111") then
D<=Radd2;
elsif(code = "1000") then
D<=fmulti;
else
D<=compare;
end if;
end process;



end structual;

我运行此代码并始终先运行if if和last ...为什么？

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vhdl如何在结构代码上选择信号

1 个答案: