以下代码不会更新temp_count，一个信号。

Question

我有一个10位乘法器的结构化实现，其中它们是一个控制单元，可以跟踪状态并相应地更新。他们是一个名为temp_count的计数器，它应该更新并告诉我是否完成了任务。我希望我能附上模拟图片，但我无法访问它。我稍后会更新。如果有人可以帮助我，那么这就是代码。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity  Controller  is
port (reset     : in std_logic ;
      clk       : in std_logic ;
      START     : in std_logic ;
      LSB       : in std_logic ;
      ADD_cmd   : out std_logic ;
      SHIFT_cmd : out std_logic ;
      LOAD_cmd  : out std_logic ;
      STOP      : out std_logic);
end;
architecture  rtl  of  Controller  is
signal temp_count : std_logic_vector(3 downto 0);
-- declare states
type state_typ is (IDLE, INIT, TEST, ADD, SHIFT);
signal state : state_typ;
begin
process (clk, reset)
  begin
    if reset='0' then
      state <= IDLE;
      temp_count <= "0000";
    elsif (clk'event and clk='1') then
            when IDLE =>
          if START = '1' then
            state <= INIT;
          else
            state <= IDLE;
          end if;
        when INIT =>
          state <= TEST;
        when TEST =>
          if LSB = '0' then
            state <= SHIFT;
          else
            state <= ADD;
          end if;
        when ADD =>
          state <= SHIFT;
        when SHIFT =>
          if temp_count = "1001" then  -- verify if finished
            temp_count <= "0000";      -- re-initialize counter
            state <= IDLE;            -- ready for next multiply
          else
            temp_count <= temp_count + 1; -- increment counter
            state <= TEST;
          end if;
      end case;
    end if;
  end process;
  STOP <= '1' when state = IDLE else '0';
  ADD_cmd <= '1' when state = ADD else '0';
  SHIFT_cmd <= '1' when state = SHIFT else '0';
  LOAD_cmd <= '1' when state = INIT else '0';
end rtl;