vhdl中的真值表中的错误

Question

Truth table

My code

我计算了卡诺图，但我的代码不正确。我收到错误：“错误D ='1'C ='0'B ='1'A ='0'预期O ='1'，收到O ='0'”。

我在哪里弄错了？

library IEEE;
use IEEE.std_logic_1164.all;
entity truth_table is port(   A,B,C,D : in    std_logic;
                              O       : out   std_logic);
end truth_table;  

architecture behavior of truth_table isbegin

O <= (((not A) and C and D) or ((not D) and B and C) or (A and (not C) and D) or (A and C and (not B)));
end behavior;

Answer 1

信号右侧的逻辑等式＆＃39; O＆＃39;是错的应该是：

O <= (((not D) and B and A) or ((not A) and C and B) or (D and (not B) and A) or (D and B and (not C)));

请参阅http://www.32x8.com/var4.html并自行尝试，但请注意列的排序与真值表中的顺序相反。