调试测试台,StX输出

时间:2016-10-25 04:52:01

标签: verilog

我一直试图让波形正确输出2n位字比较器的正确表达式,但输出每次给我一条StX和红线。我知道这是驱动信号的一个问题,我已经将大部分输出更改为reg而不是连线,因此正确的驱动器将转到正确的输出,但无济于事。

 module nbitcomparefinal #(
 parameter n = 4
 )(input clk,
   input [(2*n-1):0]x,
   input [(2*n-1):0]y,
   output reg xgy,
   output reg xey,
   output reg xly
 );

wire [n:0] xgy_w,xey_w,xly_w;

assign xgy_w[n] = 0;
assign xey_w[n] = 0;
assign xly_w[n] = 0; 

        generate
            genvar i;
            for (i=0;i<n;i=i+1)
            begin:twobitcomp
                    twobitcomp u_1 
                    (.xgyin(xgy_w[i+1]),                        
                    .xeyin(xey_w[i+1]),
                    .xlyin(xly_w[i+1]),
                    .x(x[(2*i+1) : (2*i)]),
                    .y(y[(2*i+1) : (2*i)]),
                    .xgy(xgy_w[i]),
                    .xey(xey_w[i]),
                    .xly(xly_w[i]),
                    .clk(clk));
            end
            endgenerate

always @(*) begin
 xgy = xgy_w[0];
 xey = xey_w[0];
 xly = xly_w[0];
end
endmodule

下面列出了下层模块twobitcomp。

module twobitcomp(xgyin, xeyin, xlyin, x, y, xgy, xey, xly, clk);
input clk;
input [1:0] x, y;
input xgyin, xeyin, xlyin;
output xgy, xey, xly;
reg xgy, xey, xly;

always @(*)
if (xgyin)
  begin xgy = 1'b1; xey = 1'b0; xly = 1'b0; end
 else if (xlyin)
  begin xgy = 1'b0; xey = 1'b0; xly = 1'b1; end
 else if (xeyin)
  begin
    xgy = (x[1]&~y[1])|(x[1]&x[0]&~y[0])|(x[0]&~y[1]&~y[0]);
    xey = (x[1]~^y[1])&(x[0]~^y[0]);
    xly = (~x[1]&~x[0]&y[0])|(~x[1]&y[1])|(~x[0]&y[1]&y[0]);
  end
 else
  begin xgy = 1'bx; xey = 1'bx; xly = 1'bx;
  end
endmodule

这就是我的测试平台。 for循环模仿x和y的8位字。

`timescale 1ns/1ns
module nbitcomparefinal_tb();

parameter n = 4;
reg clk;
reg [15:0] count;
wire [7:0] x, y;

wire xgy, xey, xly;

initial begin
 clk = 1;
 count = -1;
end
always #5 clk = ~clk;
always @(posedge clk)
 count = count + 1;

 nbitcomparefinal MUT(clk, x, y, xgy, xey, xly);
 genvar i;
  for(i = 0; i < 8; i = i+1)
  begin 
   assign x[i] = count[i+8];
   assign y[i] = count[i];
  end 
endmodule

这是我的波形。

enter image description here

0 个答案:

没有答案