这是同步类型计数器的VHDL代码。由于我还是vhdl的新手,我在编写测试平台时遇到了模拟此代码的问题。谁能给我一些关于如何编写测试平台的建议?谢谢
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity cnt4 is
port( CLK, RST : in std_logic;
Q : out std_logic);
end cnt4;
architecture EX1 of cnt4 is
signal cnt : std_logic_vector(1 downto 0);
begin
process(CLK, RST)
begin
if RST = '1' then
cnt <= "00";
elsif CLK'event and CLK = '1' then
if cnt = 3 then
cnt <= "00";
Q <= '1';
else
cnt <= cnt + 1;
Q <= '0';
end if;
end if;
end process;
end EX1;
这是我到目前为止尝试编写的测试平台
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity TESTBENCH is
end TESTBENCH;
architecture EX1 of TESTBENCH is
signal CLK, RST : std_logic;
signal Q : std_logic;
component cnt4
port( CLK, RST : in std_logic;
Q : out std_logic );
end component;
begin
U0: cnt4 port map(CLK, RST, Q);
process
begin
CLK <= '1';
wait for 10 ns;
CLK <= '0';
wait for 10 ns;
wait;
end process;
process
begin
RST <= '0'; wait for 10 ns;
RST <= '1'; wait for 10 ns;
wait;
end process;
end EX1;
使用上面的测试平台的模拟结果如图所示
它可能看起来很荒谬,因为我真的不知道如何编写测试平台。如果有人能帮助我会很高兴