Question

Port ( 
           data_out : out integer range -128 to 127
type ramtype is array (0 downto 29) of integer range -128 to 127;
signal ram : ramtype;
signal sine_wave : ramtype :=(0,16,31,45,58,67,74,77,77,74,67,58,45,31,16,0,
-16,-31,-45,-58,-67,-74,-77,-77,-74,-67,-58,-45,-31,-16);

signal clk :STD_LOGIC;
variable count : integer := 0;
variable inc : integer := 0; 
constant period :time := 10 ms;   -- 100 hz clk frequency 
begin
 process(clk)
 begin
    if rising_edge (clk) then

LINE：53 inc＆lt; = inc + 1; - 错误因为我在0到29循环 data_out＆lt; = sine_wave（count）;
结束循环;

    end if;

结束过程;

LINE 61：process（inc）
开始

    clk <= not clk after period/2;

 end process;

第53行：使用：=分配给变量inc 第61行：灵敏度列表只能有静态信号名称

我需要第53行的并发stetment编译器建议另一个东西，并且灵敏度列表也不被接受第61行：灵敏度列表只能有静态信号名称

Answer 1

我想生成一个正弦波，我的clk频率是100赫兹，而我想要在时钟的每个方面对其进行相应的采样

我之前这样做是为了找到您所分享的代码部分的所有问题。它还不清楚inc在时钟处理敏感性列表中做了什么。

时钟处理已被修改为仅输出一个完整的波形。请注意，inc和count都被声明为信号。

ramtype的范围方向已从0 downto 29更改为0 to 29。

我将clk的默认值设置为＆＃39; 0＆＃39;这不允许时钟不提供＆＃39; U＆＃39; （请参阅包std_logic_1164中的非真值表：

-- truth table for "not" function
CONSTANT not_table: stdlogic_1d :=
--  -------------------------------------------------
--  |   U    X    0    1    Z    W    L    H    -   |
--  -------------------------------------------------
     ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );

clk的初始值必须为＆＃39; 0＆＃39; （或＆＃39; L＆＃39;）或＆＃39; 1＆＃39; （或＆＃39; H＆＃39;）使时钟处理在模拟中工作。

您的代码片段已修改为分析，详细说明和模拟：

library ieee;
use ieee.std_logic_1164.all;

entity sinewave is
end entity;

architecture foo of sinewave is

   -- Port (
   --            data_out : out integer range -128 to 127
   signal   data_out: integer range -128 to 127;
   type ramtype is array ( integer range 0 to 29) of  -- was downto
                               integer range -128 to 127;
   -- signal ram : ramtype;
   constant sine_wave: ramtype := ( 
              0, 16, 31, 45, 58, 67, 74, 77, 77, 74, 67, 58, 45, 31, 16,
              0,-16,-31,-45,-58,-67,-74,-77,-77,-74,-67,-58,-45,-31,-16
           );

   signal clk :STD_LOGIC := '0';  --  so not clk gives '1' or '0'
   signal count : integer  range  0 to 29 :=  0;
   signal inc : integer :=  0;     
   constant period :time := 10 ms;   -- 100 hz clk frequency 
begin
    process(clk)
    begin
        if rising_edge (clk) then
LINE_53:     inc <= inc + 1;        -- error

            if count = 29 then      -- count  is index pointer to sine_wave
                count <= 0;
            else 
                count <= count + 1;
            end if ;
            -- for i in 0 to 29 loop
            data_out <= sine_wave(count);   
            report "data_out <= " & integer'IMAGE(sine_wave(count));
            --end loop;  
        end if;
     end process;  

LINE_61: process    -- modified to show every element of sine_wave once
    begin           
    wait for period/2;
    clk <= not clk;  -- after period/2;
    if Now > 29.5 * period  then
        wait;
    end if;
    end process;

end architecture;

请注意count如何用作sine_wave的索引，因此我添加了一个增量。同时拥有inc和count。

似乎是多余的

正如我在评论中解释的那样，for循环被删除了，因为它没有做任何事情，只是重复相同的sine_wave分配30次。它不会影响模拟。

因为你提供了一个时钟程序，所以我进入了测试平台。

运行报表语句时，输出count索引sine_wave值作为显示用于演示产生的显示：

ghdl -r sinewave sine.vhdl:37:13:@5ms:(report note): data_out <= 0 sine.vhdl:37:13:@15ms:(report note): data_out <= 16 sine.vhdl:37:13:@25ms:(report note): data_out <= 31 sine.vhdl:37:13:@35ms:(report note): data_out <= 45 sine.vhdl:37:13:@45ms:(report note): data_out <= 58 sine.vhdl:37:13:@55ms:(report note): data_out <= 67 sine.vhdl:37:13:@65ms:(report note): data_out <= 74 sine.vhdl:37:13:@75ms:(report note): data_out <= 77 sine.vhdl:37:13:@85ms:(report note): data_out <= 77 sine.vhdl:37:13:@95ms:(report note): data_out <= 74 sine.vhdl:37:13:@105ms:(report note): data_out <= 67 sine.vhdl:37:13:@115ms:(report note): data_out <= 58 sine.vhdl:37:13:@125ms:(report note): data_out <= 45 sine.vhdl:37:13:@135ms:(report note): data_out <= 31 sine.vhdl:37:13:@145ms:(report note): data_out <= 16 sine.vhdl:37:13:@155ms:(report note): data_out <= 0 sine.vhdl:37:13:@165ms:(report note): data_out <= -16 sine.vhdl:37:13:@175ms:(report note): data_out <= -31 sine.vhdl:37:13:@185ms:(report note): data_out <= -45 sine.vhdl:37:13:@195ms:(report note): data_out <= -58 sine.vhdl:37:13:@205ms:(report note): data_out <= -67 sine.vhdl:37:13:@215ms:(report note): data_out <= -74 sine.vhdl:37:13:@225ms:(report note): data_out <= -77 sine.vhdl:37:13:@235ms:(report note): data_out <= -77 sine.vhdl:37:13:@245ms:(report note): data_out <= -74 sine.vhdl:37:13:@255ms:(report note): data_out <= -67 sine.vhdl:37:13:@265ms:(report note): data_out <= -58 sine.vhdl:37:13:@275ms:(report note): data_out <= -45 sine.vhdl:37:13:@285ms:(report note): data_out <= -31 sine.vhdl:37:13:@295ms:(report note): data_out <= -16

您的10毫秒时钟周期意味着正弦波为3.333 .. Hz。

我正在使用lut生成一个正弦波

1 个答案: