Question

这是vhdl代码。这一个没有错误

library IEEE;
use IEEE.std_logic_1164.all;

entity sel4_1 is
   port( A, B, C, D : in std_logic;
     SEL        : in std_logic_vector(1 downto 0);
     outsgnl    : out std_logic );
   end sel4_1;

architecture EX1 of sel4_1 is
begin

process(A, B, C, D, SEL)
begin
case SEL is
   when "00" => outsgnl <= A;
   when "01" => outsgnl <= B;
   when "10" => outsgnl <= C;
   when others => outsgnl <= D;
end case;
end process;

end EX1;

这是具有错误

的测试平台

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity TESTBENCH is
end TESTBENCH;

architecture RTL of TESTBENCH is

component sel4_1

   port(A,B,C,D : in std_logic_vector(7 downto 0);
        outsgnl : out std_logic);

end component;

signal INA, INB, INC, IND, OUTSGNL : std_logic_vector(7 downto 0);
signal SEL : std_logic_vector(1 downto 0);

begin
   U0: sel4_1 port map(INA, INB, INC, IND, SEL, OUTSGNL);
   process
   begin
     INA <= "11111111";
     INB <= "11110000";
     INC <= "00001111";
     IND <= "00000000";

     SEL <= "00"; wait for 10 ns;
     SEL <= "01"; wait for 10 ns;
     SEL <= "10"; wait for 10 ns;
     SEL <= "11"; wait for 10 ns;

     wait;
   end process;
end RTL;

出现的错误是 testbench.vhdl：19：27：无法联想到＆＃39; ina＆＃39;带信号接口＆＃34; ina＆＃34;

testbench.vhdl：19：27 :(＆＃39; ina＆＃39;是std_logic的类型）

testbench.vhdl：11：9 :(信号接口的类型＆＃34; ina＆＃34;是std_logic_vector的子类型）

Answer 1

问题是您的实体sel4_1和您的组件sel_4_1不一样。您的A，B，C，D端口在第一个端口中为std_logic，在第二个端口中为std_logic_vector(7 downto 0)。

使用您真正需要的内容更改实体（或组件），它应该正常工作。

Answer 2

这是修改后的代码：

library IEEE;
use IEEE.std_logic_1164.all;

entity sel4_1 is
   port( A, B, C, D : in std_logic_vector(7 downto 0);
        SEL         : in std_logic_vector(1 downto 0);
        outsgnl     : out std_logic_vector(7 downto 0) );
   end sel4_1;

architecture EX1 of sel4_1 is
begin

process(A, B, C, D, SEL)
begin
case SEL is
   when "00" => outsgnl <= A;
   when "01" => outsgnl <= B;
   when "10" => outsgnl <= C;
   when others => outsgnl <= D;
end case;
end process;

end EX1;

测试平台：

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity TESTBENCH is
end TESTBENCH;

architecture RTL of TESTBENCH is

component sel4_1
   port(A,B,C,D : in std_logic_vector(7 downto 0);
        SEL     : in std_logic_vector(1 downto 0);
        OUTSGNL : out std_logic_vector(7 downto 0));
end component;

signal INA, INB, INC, IND, OUTSGNL : std_logic_vector(7 downto 0);
signal SEL : std_logic_vector(1 downto 0);

begin
   U0: sel4_1 port map(INA, INB, INC, IND, SEL, OUTSGNL);
   process
   begin
     INA <= "11111111";
     INB <= "11110000";
     INC <= "00001111";
     IND <= "00000000";

     SEL <= "00"; wait for 10 ns;
     SEL <= "01"; wait for 10 ns;
     SEL <= "10"; wait for 10 ns;
     SEL <= "11"; wait for 10 ns;

     wait;
   end process;
end RTL;

Answer 3

作为哈基姆（完全正确）建议的替代方案，有同样的方法可以做同样的事情。

library IEEE;
use IEEE.std_logic_1164.all;

entity sel4_1 is
   port( A, B, C, D : in std_logic_vector(7 downto 0);
        SEL         : in std_logic_vector(1 downto 0);
        outsgnl     : out std_logic_vector(7 downto 0) );
   end sel4_1;

architecture EX1 of sel4_1 is
begin

  with SEL select
    outsgnl <= A when "00",
               B when "01",
               C when "10",
               D when others;
end EX1;

我更愿意避免使用除时钟进程之外的任何进程。灵敏度列表中的缺失信号将导致模拟/合成不匹配。保持这些敏感性列表可能会变成熊。如果需要组合过程，列表应该非常小。（是的，有VHDL-2008＆＃39; all，这有帮助。）

我试图使用vhdl制作一个8位4-1选择器电路。有人可以帮我解决这段代码的错误吗？

3 个答案: