Question

我正在尝试连接带有PS / 2端口的键盘和basys 2的端口，其中显示8个LED中键的ASCII码。有这些警告：

警告：Xst：2109 - latch＆lt; tecla＆gt;的内容。电路运行期间永远不会改变锁存器被移除，信号连接到值XXXXXXXX 警告：PhysDesignRules：367 - 信号＆lt; ps2data_IBUF＆gt;不完整。信号不会驱动设计中的任何负载引脚警告：PhysDesignRules：367 - 信号＆lt; ps2clk_IBUF＆gt;不完整。信号不会驱动设计中的任何负载引脚警告：PhysDesignRules：367 - 信号＆lt; CLK_IBUF＆gt;不完整。信号不会驱动设计中的任何负载引脚警告：参数：288 - 信号ps2data_IBUF无负载。 PAR不会尝试路由此信号警告：参数：288 - 信号ps2clk_IBUF无负载。 PAR不会尝试路由此信号警告：参数：288 - 信号CLK_IBUF无负载。 PAR不会尝试路由此信号警告：参数：283 - 此设计中有3个无负载信号。此设计将导致Bitgen发出DRC警告。

代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity teclado is
Port ( 
    ps2data :  in  STD_LOGIC;
    datoslcd : out STD_LOGIC_VECTOR (7 downto 0);
    CLKINT :   in  STD_LOGIC;
    ps2clk :   in  STD_LOGIC
);
end teclado;

architecture Behavioral of teclado is

    signal start:    std_logic;
    signal paridad : std_logic;
    signal stop :    std_logic;
    signal datos :   STD_LOGIC_VECTOR (7 downto 0);

    signal vpar :    std_logic;

    signal reset:     std_logic;    
    signal enablevalidador : std_logic;

    signal timeoutor : std_logic;

    signal teclacorrecta,resetvalidador: std_logic;

    signal tecla : std_logic_vector(7 downto 0);

    signal datostemp : std_logic_vector (10 downto 0);
    signal contador :  integer range 0 to 10;
    signal enable :    std_logic;

    signal contador2 : integer range 0 to 10;
    signal cont_divdefreq : integer range 0 to 3000;
    signal clkdiv : std_logic;

begin

-------------------------------------------
-------registro de dezplazamiento----------
-------------------------------------------

    start <= datostemp(10);
    datos <= datostemp(9) & datostemp(8) & datostemp(7) & datostemp(6) & datostemp(5) & datostemp(4) & datostemp(3) & datostemp(2);
    paridad <= datostemp(1);
    stop <= datostemp(0);

process (ps2data, ps2clk)
begin
    if ps2clk'event and ps2clk = '1' then
        datostemp(0)  <= datostemp(1);
        datostemp(1)  <= datostemp(2);
        datostemp(2)  <= datostemp(3);
        datostemp(3)  <= datostemp(4);
        datostemp(4)  <= datostemp(5);
        datostemp(5)  <= datostemp(6);
        datostemp(6)  <= datostemp(7);
        datostemp(7)  <= datostemp(8);
        datostemp(8)  <= datostemp(9);
        datostemp(9)  <= datostemp(10);
        datostemp(10) <= ps2data;
    end if;
end process;

-------------------------------------
------ verificador de paridad--------
-------------------------------------

process (datos, paridad)
begin
    if((datos(0) xor datos(1) xor datos(2) xor datos(3) xor datos(4) xor datos(5) xor datos(6) xor datos(7)) = paridad) then
        vpar <= '1';
    else 
        vpar <= '0';
    end if;
end process;

------------------------------
-------contador 0 a 10--------
------------------------------

enablevalidador <= enable;

process (ps2clk, reset)
begin 
    if reset = '1' then
        contador <= 0;
        enable <= '0';
    else
        if ps2clk'event and ps2clk ='1' then
            contador <=  contador + 1;
            enable <= '0';
            if contador >= 10 then
                contador <= 0;
                enable <= '1';
            else
                contador <= contador;
                enable <= '0';
            end if;
        else
            contador <= contador;
            enable <= enable;
        end if;
    end if;
end process;

-----------------------------
----------time out-----------
-----------------------------

process (ps2clk, clkdiv)
begin
    if ps2clk'event and ps2clk = '1' then
        if clkdiv'event and clkdiv = '1' then
            contador2 <= contador2 + 1 ;
            if contador2 >= 4 then
                timeoutor <= '1' ;
                contador2 <= 0;
            else
                timeoutor <= '0';
                contador2 <= contador2;
            end if;
        end if;
    end if;
end process;

process (CLKINT)
begin 
    if  CLKINT'event and CLKINT ='1' then
        cont_divdefreq <=  cont_divdefreq + 1;
        if cont_divdefreq > 1249 then
            cont_divdefreq <= 0;
            clkdiv <= not clkdiv;
        end if;
    end if;
end process;

--------------------------------
----------validador-------------
--------------------------------

process (enablevalidador, start, stop,vpar)
begin
    if enablevalidador='1' then
        if (start = '0') and (stop = '1') and (vpar = '1') then
            teclacorrecta <= '1';
            resetvalidador <= '0';
        else
            teclacorrecta <= '0';
            resetvalidador <= '1';
        end if;
    else 
        teclacorrecta <= '0';
        resetvalidador <= '0';
    end if;
end process;

---------------------------------
---------memoria tecla-----------               
---------------------------------

process (teclacorrecta, datos)
begin
    if teclacorrecta'event and teclacorrecta = '1' then
        tecla <= datos;
    end if;
end process;

-------------------------------------
-----codificador tecla a ascii-------
-------------------------------------

process (tecla)
begin
    if tecla = "00011100" then
        datoslcd <= "01000001";
    elsif tecla = "00110010" then
        datoslcd <= "01000010";     
    else
        datoslcd <= "00000000";
    end if;
end process;

--------------------------
-------or reset-----------
--------------------------

    reset <= timeoutor or resetvalidador;

end Behavioral;

我的UCF：

    NET "datoslcd[0]" LOC = M5;
    NET "datoslcd[1]" LOC = M11;
    NET "datoslcd[2]" LOC = P7;
    NET "datoslcd[4]" LOC = N5;
    NET "datoslcd[3]" LOC = P6;
    NET "datoslcd[5]" LOC = N4;
    NET "datoslcd[6]" LOC = P4;
    NET "datoslcd[7]" LOC = G1;
    NET "CLK" LOC = B8;
    NET "ps2clk" LOC = B1;
    NET "ps2data" LOC = C3;

请

ISE XILINX PhysDesignRules：367 - 信号＆lt;＆gt;不完整。信号不会驱动设计中的任何负载引脚

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