Question

我正在用verilog设计一个简单的流水线处理器。我认为我的代码很好，但是当我运行我的测试台时没有任何反应。我实例化了所有变量但是我的always块似乎被忽略了。我有下面的处理器代码和测试平台的副本。

处理器：

module Processor(output [0:15]pc, output [0:31]Instruction, output [0:31] readData1, output [0:31]readData2, output clk
);
// IF Stuff
reg clk, PCSrc;
reg [0:15]pc;
reg [0:15]add;
reg [0:15]jump;
wire [0:31]Instruction;

// ID Stuff
reg [0:1]ControlWB;
reg [0:2]ControlM;
reg [0:3]ControlEX;
reg [0:31]SignExtend;
reg [0:31]Instruction_ID;
reg [0:15]pc_ID;

// EX Stuff
reg [0:4]RegDst;
reg [0:31]readData2Out;
reg [0:31]ALUresult;
reg [0:31]AddResult;
reg Zero;
reg [0:2]ControlM_EX;
reg [0:1]ControlWB_EX;
reg [0:3]ControlEX_EX;
reg [0:31]SignEX;
reg [0:15]pc_EX;
reg [0:31]Instruction_EX;
reg [0:31]readData1_EX;
reg [0:31]readData2_EX;

// MEM Stuff
reg [0:2]ControlM_MEM;
reg [0:1]ControlWB_MEM;
reg [0:31]dmAddress;
reg [0:31]writeData;

// WB Stuff
reg [0:31]wbData0;
reg [0:31]wbData1;
reg RegWrite;
reg [0:31]WriteData;
// Sub Modules
InstructionMem im(clk, pc, Instruction);
Register regMain(clk,Instruction_ID, Instruction_ID, RegWrite, writeData,writeReg,readData1,readData2);
DataMem dm(clk,dmAddress,writeData,ControlM_MEM[0],ControlM_MEM[1],ReadData);


/*initial begin
    pc = 0;
    PCSrc = 0;
    add = 0;
end*/

//always begin
//  #5 clk = ~clk;
//end


// IF Stage 
assign Instruction = Instruction_ID;
always @(posedge clk) begin

    case(PCSrc)
        1'b0: pc = add;
        1'b1: pc = jump;
        default: pc = add;
    endcase
    add = add + 3'b100;
    pc_ID = add;
end
// end IF

// ID begin
always @(posedge clk) begin
    casez(Instruction_ID)  // Case for determining control values
    32'b000000zzzzzzzzzzzzzzzzzzzzzzzzzz: begin // R-Type
         ControlWB = 2'b01;
         ControlM = 3'b000;
         ControlEX = 4'b0101;
        end
    32'b000100zzzzzzzzzzzzzzzzzzzzzzzzzz: begin // BEQ
         ControlWB = 2'bz0;
         ControlM = 3'b001;
         ControlEX = 4'b001x;
        end
    32'b100011zzzzzzzzzzzzzzzzzzzzzzzzzz: begin // LW
         ControlWB = 2'b11;
         ControlM = 3'b100;
         ControlEX = 4'b1000;
        end
    32'b101011zzzzzzzzzzzzzzzzzzzzzzzzzz: begin // SW
         ControlWB = 2'bz0;
         ControlM = 3'b010;
         ControlEX = 4'b100x;
        end
    endcase

    if (Instruction_ID[15] == 0) SignExtend = Instruction_ID & 32'b00000000000000001111111111111111;
    else  SignExtend = Instruction_ID | 32'b11111111111111110000000000000000;
    ControlWB_EX = ControlWB;
    ControlM_EX = ControlM;
    ControlEX_EX = ControlEX;
    SignEX = SignExtend;
    pc_EX = pc_ID;
    Instruction_EX = Instruction_ID;
    readData1_EX = readData1;
    readData2_EX = readData2;
end
// ID end

// EX begin
always @(posedge clk) begin
        casez(ControlEX_EX)
            4'bz00z:  ALUresult = readData1_EX + SignExtend;// LW/SW
            4'bz01z: if (readData1_EX == readData2_EX)// BEQ
                            Zero = 1;
                        else
                            Zero = 0;
            4'bz1zz: begin // R-Type
                casez(SignEX)
                    32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzz0000:  ALUresult = readData1_EX + readData2_EX;
                    32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzz0010:  ALUresult = readData2_EX - readData1_EX;
                    32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzz0100:  ALUresult = readData1_EX & readData2_EX;
                    32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzz0101:  ALUresult = readData1_EX | readData2_EX;
                    32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzz1010: begin  
                                                                            if (readData1_EX < readData2_EX)
                                                                                 ALUresult = 1;
                                                                            else
                                                                                 ALUresult = 0;
                    end
                endcase
            end
        endcase

        casez(ControlEX_EX)
            4'bzzz0:  RegDst = Instruction [16:20];
            4'bzzz1:  RegDst = Instruction [11:15];
        endcase
        AddResult = pc_EX + (SignEX * 4);
        readData2Out = readData2;
        ControlM_MEM = ControlM_EX;
        ControlWB_MEM = ControlWB_EX;
        jump = AddResult;
        dmAddress = ALUresult;
        writeData = readData2_EX;
end
// EX end

// MEM begin
always @(posedge clk) begin
    if (ControlM_MEM == 3'bxx1 && Zero == 1) begin
         PCSrc = 1'b1;
    end
    wbData1 = dmAddress;
    wbData0 = ReadData;
end
// MEM end

// WB begin
always @(posedge clk) begin

    casez(ControlWB)
        2'b0z:  WriteData = wbData0;
        2'b1z:  WriteData = wbData1;
    endcase
     RegWrite = ControlWB[1];
end
// WB end

endmodule

试验台：

module Processor_tf;

// Outputs
reg [0:15] pc;
wire [0:31] Instruction;
reg clk,PCSrc;
reg [0:15]add;

// Instantiate the Unit Under Test (UUT)
Processor uut (
    .pc(pc), 
    .Instruction(Instruction),
    .clk(clk)
);

initial begin
    // Initialize Inputs
    clk = 0;
    pc = 16'b0;
    PCSrc = 0;
    add = 16'b100;
    // Wait 100 ns for global reset to finish
    #100;

    // Add stimulus here

end

always begin
    #5 clk = ~clk;
end

endmodule

Answer 1

没有clk附加到module Processor，实际上你的逻辑无论如何都没有被运用。您已将clk定义为处理器的输出，而不是在模块内生成。 clk在testbench中生成。简而言之： - 模块没有时钟，因为未生成clk。 Testbecn正在生成clk，它在任何地方都没有连接。

将clk定义为处理器中的输入，并将时钟从testbench附加到它。

测试台代码在管道处理器的verilog中不起作用

1 个答案: