Question

library ieee;
use ieee.std_logic_1164.all;

entity alu_1bit is
  port (
    i_OPERATION : in  std_logic_vector(1 downto 0);  -- entrada de operação (controle de operação)
    i_INV_BIT   : in  std_logic;
    i_CARRY_IN  : in  std_logic;
    i_A         : in  std_logic;
    i_B         : in  std_logic;
    i_LESS      : in  std_logic;
    o_RESULT    : out std_logic;
    o_CARRY_OUT : out std_logic);
end alu_1bit;

architecture arch_1 of alu_1bit is
  component full_adder is
    port (
      i_CIN  : in  std_logic;
      i_DIN0 : in  std_logic;
      i_DIN1 : in  std_logic;
      o_DOUT : out std_logic;
      o_COUT : out std_logic);
  end component;

  component mux4 is
    port(i_SEL  : in  std_logic_vector(1 downto 0);
         i_DIN0 : in  std_logic;
         i_DIN1 : in  std_logic;
         i_DIN2 : in  std_logic;
         i_DIN3 : in  std_logic;
         o_DOUT : out std_logic);
  end component;

  signal w_B     : std_logic;
  signal w_C     : std_logic;
  signal w_D     : std_logic;
  signal w_OUTFA : std_logic;

begin
  w_B <= i_INV_BIT xor i_B;
  w_C <= i_A and i_B;
  w_D <= i_A or i_B;

  u_1 : full_adder port map (i_CIN  => i_CARRY_IN,
                             i_DIN0 => i_A,
                             i_DIN1 => w_B,
                             o_DOUT => w_OUTFA,
                             o_COUT => o_CARRY_OUT);

  u_2 : mux4 port map(i_SEL  => i_OPERATION,
                      i_DIN0 => w_C,
                      i_DIN1 => w_D,
                      i_DIN2 => w_OUTFA,
                      i_DIN3 => i_LESS,
                      o_DOUT => o_RESULT);

end arch_1;

我试图在Quartus ModelSim上模拟这个，但在ModelSim上给我以下错误。

错误：... / alu_1bit_msb.vhd（53）:( vcom-1436）形式＆＃34; i_DIN0＆＃34;的实际表达式（中缀表达式）并非全球静态。

错误：... / alu_1bit_msb.vhd（54）:( vcom-1436）形式＆＃34; i_DIN1＆＃34;的实际表达式（中缀表达式）并非全球静态。

我已经从mux4的端口映射中删除了逻辑表达式，我用信号做了这个...

完整的地址代码：

library ieee;
use ieee.std_logic_1164.all;

entity full_adder is
port (
    i_CIN : in std_logic;
    i_DIN0 : in std_logic; 
    i_DIN1 : in std_logic; 
    o_DOUT : out std_logic; 
    o_COUT : out std_logic); 
end full_adder;

architecture arch_1 of full_adder is
begin
    o_DOUT <= i_CIN xor i_DIN0 xor i_DIN1;
    o_COUT <= (i_CIN and i_DIN0) or
    (i_CIN and i_DIN1) or
    (i_DIN0 and i_DIN1);
end arch_1;

MUX4代码：

library ieee;
use ieee.std_logic_1164.all;

entity mux4 is
port (
    i_SEL : in std_logic_vector(1 downto 0); 
    i_DIN0 : in std_logic;
    i_DIN1 : in std_logic;
    i_DIN2 : in std_logic; 
    i_DIN3 : in std_logic; 
    o_DOUT : out std_logic); 
end mux4;

architecture arch_1 of mux4 is
begin
    o_DOUT <= i_DIN0 when i_SEL = "00" else
          i_DIN1 when i_SEL = "01" else
          i_DIN2 when i_SEL = "10" else
          i_DIN3;
end arch_1;

alu32代码：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;

entity alu_32bit is
port (
    i_OPERATION :   in  std_logic_vector(1 downto 0);       
    i_INV_BIT   :   in      std_logic;
    i_A         :   in  std_logic_vector(31 downto 0);
    i_B         :   in  std_logic_vector(31 downto 0);
    o_RESULT        :   out std_logic_vector(31 downto 0);
    o_ZERO      :   out std_logic;
    o_OVERFLOW  :   out std_logic);
end alu_32bit;

architecture arch_1 of alu_32bit is
    component alu_1bit is
    port (
        i_OPERATION :   in std_logic_vector(1 downto 0);        
        i_INV_BIT   :   in std_logic;
        i_CARRY_IN  :   in std_logic;
        i_A         :   in std_logic;
        i_B         :   in std_logic;
        i_LESS      : in std_logic;
        o_RESULT        :   out std_logic;
        o_CARRY_OUT :   out std_logic);
    end component;

    component alu_1bit_msb is
    port (
        i_OPERATION :   in std_logic_vector(1 downto 0);        -- entrada de operação (controle de operação)
        i_INV_BIT   :   in std_logic;
        i_CARRY_IN  :   in std_logic;
        i_A         :   in std_logic;
        i_B         :   in std_logic;
        i_LESS      :   in std_logic;
        o_RESULT        :   out std_logic;
        o_SET       :   out std_logic;
        o_OVERFLOW  :   out std_logic);
    end component;

    signal w_RESULT : std_logic_vector(31 downto 0);
    signal w_CARRY : std_logic_vector(30 downto 0);
    signal w_SET : std_logic;

begin
    o_RESULT <= w_RESULT;
    o_ZERO <= NOT (or_reduce(w_RESULT));

    u_0: alu_1bit port map (i_OPERATION => i_OPERATION,     
                                    i_INV_BIT   => i_INV_BIT,
                                    i_CARRY_IN  => i_INV_BIT,
                                    i_A         => i_A(0),
                                    i_B         => i_B(0),
                                    i_LESS      => w_SET,
                                    o_RESULT        => w_RESULT(0),
                                    o_CARRY_OUT => w_CARRY(0));

    f_0: for i in 1 to (30) generate
        u_1: alu_1bit port map (i_OPERATION => i_OPERATION,     
                                        i_INV_BIT   => i_INV_BIT,
                                        i_CARRY_IN  => w_CARRY(i-1),
                                        i_A         => i_A(i),
                                        i_B         => i_B(i),
                                        i_LESS      => '0',
                                        o_RESULT        => w_RESULT(i),
                                        o_CARRY_OUT => w_CARRY(i));
    end generate f_0;

    u_2: alu_1bit_msb port map (i_OPERATION => i_OPERATION,     
                     i_INV_BIT      => i_INV_BIT,
                                         i_CARRY_IN     => w_CARRY(30),
                                         i_A                => i_A(31),
                                         i_B                => i_B(31),
                                         i_LESS         => '0',
                                         o_RESULT           => w_RESULT(31),
                                         o_SET              => w_SET,
                                         o_OVERFLOW     => o_OVERFLOW);
end arch_1;

alu_1bit_msb代码：

library ieee;
use ieee.std_logic_1164.all;

entity alu_1bit_msb is
port (
    i_OPERATION :   in std_logic_vector(1 downto 0);        
    i_INV_BIT   :   in std_logic;
    i_CARRY_IN  :   in std_logic;
    i_A         :   in std_logic;
    i_B         :   in std_logic;
    i_LESS      :   in std_logic;
    o_RESULT        :   out std_logic;
    o_SET       :   out std_logic;
    o_OVERFLOW  :   out std_logic);
end alu_1bit_msb;

architecture arch_1 of alu_1bit_msb is
    component full_adder is
    port (
        i_CIN : in std_logic; 
        i_DIN0 : in std_logic; 
        i_DIN1 : in std_logic; 
        o_DOUT : out std_logic; 
        o_COUT : out std_logic); 
    end component;

    component mux4 is
    port(i_SEL : in std_logic_vector(1 downto 0); 
          i_DIN0 : in std_logic; 
          i_DIN1 : in std_logic; 
          i_DIN2 : in std_logic; 
          i_DIN3 : in std_logic; 
          o_DOUT : out std_logic); 
    end component;

    signal w_B : std_logic;
    signal w_OUTFA : std_logic;
    signal w_COUT : std_logic;

begin
    w_B <= i_INV_BIT XOR i_B;
    o_SET <= w_OUTFA;
    o_OVERFLOW <= (w_COUT XOR i_CARRY_IN) AND i_OPERATION(1);

    u_1: full_adder port map (i_CIN => i_CARRY_IN,
                                      i_DIN0 => i_A,
                                      i_DIN1 => w_B,
                                      o_DOUT => w_OUTFA,
                                    o_COUT => w_COUT);

    u_2: mux4 port map(
                i_SEL => i_OPERATION,       
                            i_DIN0 => i_A AND i_B,  
                            i_DIN1 => i_A OR i_B,   
                            i_DIN2 => w_OUTFA,          
                          i_DIN3 => i_LESS,         
                            o_DOUT => o_RESULT);                                      
end arch_1;

Answer 1

你是否意识到你最初在你的问题中发布了alu_1bit_msb.vhd，同时向我们显示错误消息？对观众的困惑是可以原谅的。文件名不需要与其中的声明有任何关系。

无论如何，您在alu_1bit中的修正也应该放在alu_1bit_msb中：

architecture arch_1 of alu_1bit_msb is
    component full_adder is
    port (
        i_CIN : in std_logic; 
        i_DIN0 : in std_logic; 
        i_DIN1 : in std_logic; 
        o_DOUT : out std_logic; 
        o_COUT : out std_logic); 
    end component;

    component mux4 is
    port(i_SEL : in std_logic_vector(1 downto 0); 
          i_DIN0 : in std_logic; 
          i_DIN1 : in std_logic; 
          i_DIN2 : in std_logic; 
          i_DIN3 : in std_logic; 
          o_DOUT : out std_logic); 
    end component;

    signal w_B : std_logic;
    signal w_C:     std_logic;      -- added
    signal w_D:     std_logic;      -- added
    signal w_OUTFA : std_logic;
    signal w_COUT : std_logic;

begin

    w_B <= i_INV_BIT XOR i_B;

    o_SET <= w_OUTFA;

    w_C <= i_A and i_B;  -- added
    w_D <= i_A or i_B;   -- added

    o_OVERFLOW <= (w_COUT XOR i_CARRY_IN) AND i_OPERATION(1);

    u_1: full_adder port map (i_CIN => i_CARRY_IN,
                                      i_DIN0 => i_A,
                                      i_DIN1 => w_B,
                                      o_DOUT => w_OUTFA,
                                    o_COUT => w_COUT);

    u_2: mux4 port map(
                i_SEL => i_OPERATION,       
                            i_DIN0 => w_C, -- was i_A AND i_B,
                            i_DIN1 => w_D, -- was i_A OR i_B,
                            i_DIN2 => w_OUTFA,
                          i_DIN3 => i_LESS,
                            o_DOUT => o_RESULT);    
end arch_1;

你的arch_1 of alu_1bit_msb分析（alu_1bit_msb.vhd应该用vcom编译）。

之后，如果您遇到不同的问题，请提出另一个问题，请提供MCVe，以便重现问题。

VHDL输入不是全局静态的

1 个答案: