Question

我正在尝试为BCD VHDL模块开发一个8位二进制文件，但是Xilinx套件正在优化我的Bin_in信号，以便始终接地。我发现其他几个线程提到了类似的问题（在不同的编码环境中），但提供的答案似乎涉及算法，其中未声明输出的完整真值表。我还找到了一个8位到BCD转换器的例子，其算法和我的类似。如果我正确开发了我的代码，那么当Bin_in输入发生变化时，该过程应该会运行，所以我不明白为什么这些工具会优化它。非常感谢任何信息或帮助。

这是综合警告：

WARNING:Xst:647 - Input <Bin_in<7:1>> is never used. This port will be
preserved and left unconnected if it belongs to a top-level block or
it belongs to a sub-block and the hierarchy of this sub-block is
preserved.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;

entity B8_to_4BCD is
port (Bin_in : in std_logic_vector (7 downto 0);
      BCD0, BCD1, BCD2 : out std_logic_vector (3 downto 0)
     );

end entity B8_to_4BCD;

architecture Behavioral of B8_to_4BCD is

begin

--Sequential code follows, runs if Bin_in changes
process (Bin_in)
--Holders for Bin_in and output BCD
variable input : std_logic_vector (7 downto 0);
variable output : std_logic_vector (11 downto 0);

begin
    input  := Bin_in;          --Assign Bin_in to input
    output := (others => '0'); --Set output to all zeroes

    for I in 1 to 8 loop
        --Check ones for greater than or equal to 5
        if output(3 downto 0) >= "0101" then
            output(3 downto 0) := output(3 downto 0) + "0011";

        --Check tens for greater than or equal to 5
        elsif output(7 downto 4) >= "0101" then
            output(7 downto 4) := output(7 downto 4) + "0011";

        --Check hundreds for greater than or equal to 5
        elsif output(11 downto 8) >= "0101" then
            output(11 downto 8) := output(11 downto 8) + "0011";
        else

        end if;

        output := output(11 downto 1) & input(7); --Shift output left one and move input(7) into LSB
        input := input(6 downto 0) & '0';         --Shift input left one and pad with zero

    end loop;

    BCD0 <= output(3 downto 0);
    BCD1 <= output(7 downto 4);
    BCD2 <= output(11 downto 8);

end process;

end Behavioral;

Answer 1

除了Paebbels提出的问题，if语句应该是独立的，还有一个问题就是输出的左移。

以下是更正的循环：

    for i in 1 to 8 loop
        if output(3 downto 0) >= "0101" then
            output(3 downto 0) := output(3 downto 0) + "0011";
        end if;
        --check tens for greater than or equal to 5
        if output(7 downto 4) >= "0101" then
            output(7 downto 4) := output(7 downto 4) + "0011";
        end if;
        --check hundreds for greater than or equal to 5
        if output(11 downto 8) >= "0101" then
            output(11 downto 8) := output(11 downto 8) + "0011";            
        end if;
        output := output(10 downto 0) & input(7);       --shift output left one and move input(7) into lsb
        input := input(6 downto 0) & '0' ;              --shift input left one and pad with zero;
     end loop;

使用测试平台：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bin8bcd_tb is
end entity;

architecture foo of bin8bcd_tb is
    signal bin: std_logic_vector (7 downto 0) := (others => '0');
    -- (initialized to prevent those annoying metavalue reports)

    signal bcd: std_logic_vector (11 downto 0);

begin

DUT:
    entity work.b8_to_4bcd
        port map (
            bin_in => bin,
            bcd0 => bcd(3 downto 0),
            bcd1 => bcd(7 downto 4),
            bcd2 => bcd(11 downto 8)
        );

STIMULUS:
    process

    begin
        for i in 0 to 255 loop
            bin <= std_logic_vector(to_unsigned(i,8));
            wait for 1 ns;
        end loop;
        wait for 1 ns;
        wait;
    end process;
end architecture;

给出：

（点击）

匹配输入二进制（十进制小数）和输出BCD（十六进制）的值。

您希望合成输出与模拟匹配。注意警告告诉你Bin_in＆lt; 7：1＆gt;没有改变，LSB做了（这与你的模拟相匹配，与我的相符）。

合成前的模拟适用于我们这些在校对时很糟糕的人。

vhdl输入未使用

1 个答案: