Question

我正在尝试学习之前完成C ++的verilog。作为一个学习练习，我试图在看到10个按钮后闪烁LED。我还有一个额外的重置按钮，可以再次启动10个计数。我试过什么我无法编译。有人能指出我正确的方向吗？

我的代码是：

module led_counter (button, nreset, led);

input button, nreset; 
output led;
reg counter[4:0];           // to hold the current count

always @ (negedge nreset) begin
    counter <= 0;           // Just reset counter
end

always @ (negedge button) begin

    if (counter == 10) begin // see if the button has been pressed 10 times
        led_state <= 1;      // turn the led on
    end

    else begin 
    led_state <= 0;          // the led is off
    counter <= counter + 1; 
    end

end

assign led = led_state;

endmodule

Answer 1

led_state 未声明，应为 reg 。

为了让事情更简洁，我还将两个流程重组为一个。它会使它看起来像是一个具有异步复位的同步过程，即由时钟触发并在复位的下降沿重置。

always @ (posedge button or negedge nreset) begin
    if(~nreset)       //reset counter when nreset is low
        counter <= 0;
    else begin        //do something on posedge of button
      //Do something//
end //end process

它也更有可能被合成。

Verilog if语句赋值错误

1 个答案: