Verilog ISE编译器错误：if语句附近的语法错误

Question

以下是我的代码：

task CheckTxDataFunc;
 input  [39:0] ExpectPattern0;
 input  [39:0] ExpectPattern1;
 output reg CheckTxDataFunc_Bit;
 reg Equal00;
 reg Equal01;
 reg Equal10;
 reg Equal11;

 begin
    CompareTxData(ExpectPattern1, ExpectPattern0, Equal11, Equal00);  
    CompareTxData(ExpectPattern0, ExpectPattern1, Equal01, Equal10);  
    CheckTxDataFunc_Bit = (Equal11 & Equal00) | (Equal10 &       Equal01);                            
 end
endtask

reg              checktxdata_bit;

initial begin

CheckTxDataFunc(64'h0000_0000__0000_1110, 64'h0000_0000__0000_2222, checktxdata_bit)
**if (checktxdata_bit) begin**
   $display("Message at time : %t ,Transmit data held", $time);
   end
else begin
   TestError = TestError + 1;
   $display("Error: Held transmit data incorrect. Expect %h %h, Received %h %h", TxPattern1, TxPattern0, 64'h0000_0000__0000_1110, 64'h0000_0000__0000_2222);
   end

end

我收到错误“行if (checktxdata_bit) begin的附近的语法错误。

请帮助，我无法弄清楚我哪里出错了。

Answer 1

在错误发生之前，你错过了分号。