case语句中“＆lt; =”附近的Verilog语法错误

Question

在这段代码中：

    reg [4:0] status_led = 5'b00100;
    case (status_led)
        default: begin                   
            if (rotation) begin
                status_led[4] <= status_led[3];
                status_led[3] <= status_led[2];
                status_led[2] <= status_led[1];
                status_led[1] <= status_led[0];
                status_led[0] <= status_led[4];
            end else if (~rotation) begin
                status_led[4] <= status_led[0];
                status_led[3] <= status_led[4];
                status_led[2] <= status_led[3];
                status_led[1] <= status_led[2];
                status_led[0] <= status_led[1];
            end
        end
    endcase

我在＆lt; =“附近收到错误”语法错误。为什么这是一个错误？