Question

我试图实施verilog程序并且大多数测试用例正在通过（1440中的1,188个）。我的问题是，我的预期溢出输出当前显示为0，而期望值应为1.

下面是两个例子，说明打印到日志中的内容是什么，预期值不正确（一直向右滚动）：

in1=1000000000000000 in2=1000000000000000 opCode=1001 result= 0111111111111111  expectedResult= 0111111111111111     overflow=0 expectedOverflow=1 in1=-32768           in2=-32768           opCode= 9 result=  32767            expectedResult=  32767               overflow=0  expectedOverflow=1

in1=1000000000000000 in2=1000000000000001 opCode=1001 result= 0111111111111111  expectedResult= 0111111111111111     overflow=0 expectedOverflow=1 in1=-32768           in2=-32767           opCode= 9 result=  32767            expectedResult=  32767               overflow=0  expectedOverflow=1

我找不到我的实施错误的确切位置。所以我想我的问题是，我究竟做错了什么？谢谢！

继承我的verilog代码的实现以供参考：

module Calculator(in1,in2,opCode,result,overflow);

input signed[15:0] in1, in2;

input[3:0] opCode;  
output reg signed[15:0] result;
output reg overflow;

always @ (*) begin
if(opCode == 0000) begin
   if(in1+in2<=32767 & in1+in2>= -32768) begin
       overflow = 0;
       end
       else
       begin
       overflow = 1;
       end
       end
end

always @ (*) begin
   if(opCode == 0001) begin
   if(in1-in2<=32767 & in1-in2>= -32768) begin
       overflow = 0;
       end
       else
       begin
       overflow = 1;
       end
       end
end

always @ (*) begin
   if(opCode == 0010) begin
   if(in1*5<=32767 & in1*5>= -32768) begin
       overflow = 0;
       end
       else
       begin
       overflow = 1;
       end
       end
end

always @ (*) begin
   if(opCode == 0011) begin
   if ((in1 % 10) == 0) begin
   overflow = 0;
end else begin
   overflow = 1;
end
   end
end

always @ (*) begin
   if(opCode == 0100) begin
   overflow = 0;
       end
end

always @ (*) begin
if(opCode == 0101) begin
   overflow = 0;
       end
end

always @ (*) begin
   if(opCode == 0110) begin
   overflow = 0;
       end
end

always @ (*) begin
   if(opCode == 0111) begin
   overflow = 0;
       end
end

always @ (*) begin
   if(opCode == 1000) begin
   if(in1 == 32767) begin
       overflow = 1;
       end
       else begin
       overflow = 0;
       end
       end
end

always @ (*) begin
   if(opCode == 1001) begin
   if(in1==-32768) begin
       overflow = 1;
       end
       else
       begin
       overflow = 0;
       end
       end
end

always @ (*) begin
case(opCode)
4'b0000: result = in1+in2; //add
4'b0001: result = in1-in2; //subtract
4'b0010: result = in1*5; //mult by 5
4'b0011: result = in1/10; //divide by 10
4'b0100: result = in1&in2; //AND
4'b0101: result = in1^in2; //XOR
4'b0110: result = in1|in2; //OR
4'b0111: result = /*((2^16)-1)-in1;*/(-(in1))-1; //complement
4'b1001: result = in1-1; //decrement
4'b1000: result = in1+1; //increment
endcase
end

endmodule

Answer 1

重新分配相同的变量将导致此类错误。尝试为你的代码添加新的变量/寄存器，你可以删除“always @ *”（在每个if情况下）并在单个程序中使用“begin ... end”格式。如果你最初“开始”并最终“结束”它将正常工作。

Verilog Testbench实现

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