VHDL自动售货机端口映射错误

时间:2015-12-12 23:35:20

标签: vhdl state-machine intel-fpga quartus

我正在做一个自动售货机项目,我唯一的问题是Seg的端口映射,我收到此错误:

  

警告:COMP96_0411: reu.vhd:(363,31):模式'out'的实际情况无法分配到'in'模式的正式“x”。
  错误:COMP96_0100: reu.vhd:(363,36):端口映射中的实际参数类型与正式端口“display”的类型不匹配。

在四个地方。

设计的最高层:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cafe_pf is Port (
    inicio: in std_logic;
    rst: in std_logic;
    ck: in std_logic;
    Unp: in std_logic;
    DoP: in std_logic;
    Ci5: in std_logic;
    DiP: in std_logic;
    Sie1: out std_logic_vector(3 downto 0);
    Sie2: out std_logic_vector(3 downto 0);
    Sie3: out std_logic_vector(3 downto 0)  ;
    Sie4: out std_logic_vector(3 downto 0)
);
end cafe_pf;

architecture behavioral of cafe_pf is
    type nombres_estados is (Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8,Q9, Q10, Q11, Q12, Q13, Q14,Q15,Q16,   Q17, Q18);
    signal estado: nombres_estados;
    signal entrada_aux: std_logic_vector (3 downto 0);

    component clk200Hz Port (
        clk_in : in STD_LOGIC;
        reset : in STD_LOGIC;
        clk_out: out STD_LOGIC
    );
    end component;

    component conta1  port(
        x: std_logic;
        clk: in std_logic;
    rst: std_logic;
    y: out std_logic);
    end component;

    component Seg7 port(
        x : in std_logic_vector(3 downto 0);
        display : out std_logic_vector(6 downto 0)
    );
    end component;

    signal ck2: std_logic;
    signal Unp1: std_logic;
    signal DoP2: std_logic;
    signal Ci52: std_logic;
    signal DiP2: std_logic;
    signal Sie11: std_logic;
    signal Sie21: std_logic;
    signal Sie31: std_logic;
    signal Sie41: std_logic;

begin
    cl: clk200hz port map(ck,rst,ck2);

    pulso_unpeso: conta1 port map(Unp,ck2,rst,Unp1)    ;
    pulso_dospesos: conta1 port map(DoP,ck,rst,DoP2)    ;
    pulso_cincopesos: conta1 port map(Ci5,ck,rst,Ci52)  ;
    pulso_Diezpesos: conta1 port map(Dip,ck,rst,DiP2)   ;

    entrada_aux<=DiP2&Ci52&DoP2&Unp1;

    process(inicio, ck2)
    begin
        if rst='1' and ck2'event then
            estado<=Q0;
        end if;

        if inicio='1' then
            estado<=Q0;
        elsif ck2='1' and ck2'event then
            case estado is
                when Q0 =>
                    case entrada_aux is
                        when "0000" => estado<=Q0;
                        when "0001" => estado<=Q1;
                        when "0010" => estado<=Q2;
                        when "0100" => estado<=Q5;
                        when "1000" => estado<=Q10;
                        when others => estado<=Q0;
                    end case;
                when Q1 =>
                    case entrada_aux is
                        when "0000" => estado<=Q1;
                        when "0001" => estado<=Q2;
                        when "0010" => estado<=Q3;
                        when "0100" => estado<=Q6;
                        when "1000" => estado<=Q11;
                        when others => estado<=Q0;
                    end case;
                when Q2 =>
                    case entrada_aux is
                        when "0000" => estado<=Q2;
                        when "0001" => estado<=Q3;
                        when "0010" => estado<=Q4;
                        when "0101" => estado<=Q7;
                        when "1010" => estado<=Q12;
                        when others => estado<=Q0;
                    end case;
                when Q3 =>
                    case entrada_aux is
                        when "0000" => estado<=Q3;
                        when "0001" => estado<=Q4;
                        when "0010" => estado<=Q5;
                        when "0101" => estado<=Q8;
                        when "1010" => estado<=Q13;
                        when others => estado<=Q0;
                    end case;
                when Q4 =>
                    case entrada_aux is
                        when "0000" => estado<=Q4;
                        when "0001" => estado<=Q5;
                        when "0010" => estado<=Q6;
                        when "0100" => estado<=Q9;
                        when "1000" => estado<=Q14;
                        when others => estado<=Q0;
                    end case;
                when Q5 =>
                    case entrada_aux is
                        when "0000" => estado<=Q5;
                        when "0001" => estado<=Q6;
                        when "0010" => estado<=Q7;
                        when "0100" => estado<=Q10;
                        when "1000" => estado<=Q15;
                        when others => estado<=Q0;
                    end case;
                when Q6 =>
                    case entrada_aux is
                        when "0000" => estado<=Q6;
                        when "0001" => estado<=Q7;
                        when "0010" => estado<=Q8;
                        when "0100" => estado<=Q11;
                        when "1000" => estado<=Q16;
                        when others => estado<=Q0;
                    end case;
                when Q7 =>
                    case entrada_aux is
                        when "0000" => estado<=Q7;
                        when "0001" => estado<=Q8;
                        when "0010" => estado<=Q9;
                        when "0100" => estado<=Q12;
                        when "1000" => estado<=Q17;
                        when others => estado<=Q0;
                    end case;
                when Q8 =>
                    case entrada_aux is
                        when "0000" => estado<=Q8;
                        when "0001" => estado<=Q9;
                        when "0010" => estado<=Q10;
                        when "0100" => estado<=Q13;
                        when "1000" => estado<=Q18;
                        when others => estado<=Q0;
                    end case;
                when Q9 =>
                    case entrada_aux is
                        when "0000" => estado<=Q0;
                        when "0001" => estado<=Q1;
                        when "0010" => estado<=Q2;
                        when "0100" => estado<=Q5;
                        when "1000" => estado<=Q10;
                        when others => estado<=Q0;
                    end case;
                when Q10 =>
                    case entrada_aux is
                        when "0000" => estado<=Q0;
                        when "0001" => estado<=Q1;
                        when "0010" => estado<=Q2;
                        when "0100" => estado<=Q5;
                        when "1000" => estado<=Q10;
                        when others => estado<=Q0;
                    end case;
                when Q11 =>
                    case entrada_aux is
                        when "0000" => estado<=Q0;
                        when "0001" => estado<=Q1;
                        when "0010" => estado<=Q2;
                        when "0100" => estado<=Q5;
                        when "1000" => estado<=Q10;
                        when others => estado<=Q0;
                    end case;
                when Q12 =>
                    case entrada_aux is
                        when "0000" => estado<=Q0;
                        when "0001" => estado<=Q1;
                        when "0010" => estado<=Q2;
                        when "0100" => estado<=Q5;
                        when "1000" => estado<=Q10;
                        when others => estado<=Q0;
                    end case;
                when Q13 =>
                    case entrada_aux is
                        when "0000" => estado<=Q0;
                        when "0001" => estado<=Q1;
                        when "0010" => estado<=Q2;
                        when "0100" => estado<=Q5;
                        when "1000" => estado<=Q10;
                        when others => estado<=Q0;
                    end case;
                when Q14 =>
                    case entrada_aux is
                        when "0000" => estado<=Q0;
                        when "0001" => estado<=Q1;
                        when "0010" => estado<=Q2;
                        when "0100" => estado<=Q5;
                        when "1000" => estado<=Q10;
                        when others => estado<=Q0;
                    end case;
                when Q15 =>
                    case entrada_aux is
                        when "0000" => estado<=Q0;
                        when "0001" => estado<=Q1;
                        when "0010" => estado<=Q2;
                        when "0100" => estado<=Q5;
                        when "1000" => estado<=Q10;
                        when others => estado<=Q0;
                    end case;
                when Q16 =>
                    case entrada_aux is
                        when "0000" => estado<=Q0;
                        when "0001" => estado<=Q1;
                        when "0010" => estado<=Q2;
                        when "0100" => estado<=Q5;
                        when "1000" => estado<=Q10;
                        when others => estado<=Q0;
                    end case;
                when Q17 =>
                    case entrada_aux is
                        when "0000" => estado<=Q0;
                        when "0001" => estado<=Q1;
                        when "0010" => estado<=Q2;
                        when "0100" => estado<=Q5;
                        when "1000" => estado<=Q10;
                        when others => estado<=Q0;
                    end case;
                when Q18 =>
                    case entrada_aux is
                        when "0000" => estado<=Q0;
                        when "0001" => estado<=Q1;
                        when "0010" => estado<=Q2;
                        when "0100" => estado<=Q5;
                        when "1000" => estado<=Q10;
                        when others => estado<=Q0;
                    end case;
                when others => estado<=Q0;
            end case;
        end if;
    end process;

    process(estado)
    begin
        case estado is
            when Q0 =>
                Sie1<="0000";
                Sie2<="0000";
                Sie3<="0000";
                Sie4<="0000";
            when Q1 =>
                Sie1<="0000";
                Sie2<="0001";
                Sie3<="0000";
                Sie4<="0000";
            when Q2 =>
                Sie1<="0000";
                Sie2<="0010";
                Sie3<="0000";
                Sie4<="0000";
            when Q3 =>
                Sie1<="0000";
                Sie2<="0011";
                Sie3<="0000";
                Sie4<="0000";
            when Q4 =>
                Sie1<="0000";
                Sie2<="0100";
                Sie3<="0000";
                Sie4<="0000";
            when Q5 =>
                Sie1<="0000";
                Sie2<="0101";
                Sie3<="0000";
                Sie4<="0000";
            when Q6 =>
                Sie1<="0000";
                Sie2<="0110";
                Sie3<="0000";
                Sie4<="0000";
            when Q7 =>
                Sie1<="0000";
                Sie2<="0111";
                Sie3<="0000";
                Sie4<="0000";
            when Q8 =>
                Sie1<="0000";
                Sie2<="1000";
                Sie3<="0000";
                Sie4<="0000";
            when Q9 =>
                Sie1<="0000";
                Sie2<="1001";
                Sie3<="0001";
                Sie4<="0000";
            when Q10 =>
                Sie1<="0001";
                Sie2<="0000";
                Sie3<="0001";
                Sie4<="0001";
            when Q11 =>
                Sie1<="0001";
                Sie2<="0001";
                Sie3<="0001";
                Sie4<="0010";
            when Q12 =>
                Sie1<="0001" ;
                Sie2<="0010";
                Sie3<="0001";
                Sie4<="0011";
            when Q13 =>
                Sie1<="0001" ;
                Sie2<="0011";
                Sie3<="0001";
                Sie4<="0100";
            when Q14 =>
                Sie1<="0001";
                Sie2<="0100";
                Sie3<="0001";
                Sie4<="0101";
            when Q15 =>
                Sie1<="0001";
                Sie2<="0101";
                Sie3<="0001";
                Sie4<="0110";
            when Q16 =>
                Sie1<="0001";
                Sie2<="0110";
                Sie3<="0001";
                Sie4<="0111";
            when Q17 =>
                Sie1<="0001";
                Sie2<="0111";
                Sie3<="0001";
                Sie4<="1000";
            when Q18 =>
                Sie1<="0001";
                Sie2<="1000";
                Sie3<="0001";
                Sie4<="1001";
        end case;
    end process;

    display_1: seg7 port map(Sie1,Sie11); ------ERROR HERE
    display_2: seg7 port map(Sie2,Sie21); ------ERROR HERE
    display_3: seg7 port map(Sie3,Sie31); ------ERROR HERE
    display_4: seg7 port map(Sie4,Sie41); ------ERROR HERE

 end behavioral;

在每个州Idisplay Sie1,2,3,4的数据,但我在端口地图行中得到了这个错误。

这是Seg7计划:

library IEEE;
use ieee.std_logic_1164.all;

entity Seg7 is port(
    x : in std_logic_vector(3 downto 0);
    display : out std_logic_vector(0 to 6)
);
end Seg7;

architecture SIMPLE1 of Seg7 is
    signal display0:std_logic_vector(0 to 6);
begin
    bcd_7seg: process(x)
    begin
        case x is
            when "0000" => display0 <= "1111110";
            when "0001" => display0 <= "0110000";
            when "0010" => display0 <= "1101101";
            when "0011" => display0 <= "1111001";
            when "0100" => display0 <= "0110011";
            when "0101" => display0 <= "1011011";
            when "0110" => display0 <= "1011111";
            when "0111" => display0 <= "1110000";
            when "1000" => display0 <= "1111110";
            when "1001" => display0 <= "1110011";
            when "1010" => display0 <= "1110111";
            when "1011" => display0 <= "0011111";
            when "1100" => display0 <= "1001110";
            when "1101" => display0 <= "0111101";
            when "1110" => display0 <= "1001111";
            when others => display0 <= "1000111";
        end case;
        display<=not display0;
    end process;
end SIMPLE1;

seg7是7段显示的程序,我真的不知道做错了什么。

更新。 13/2/2015 我添加建议的行并修复向量,这些错误消失了, 但现在我得到4个新错误。

Error: ELAB1_0008: reu.vhd : (370, 15): Cannot read output : "Sie1".
Error: ELAB1_0008: reu.vhd : (371, 16): Cannot read output : "Sie2".
Error: ELAB1_0008: reu.vhd : (372, 16): Cannot read output : "Sie3".
Error: ELAB1_0008: reu.vhd : (373, 16): Cannot read output : "Sie4".

新代码: 设计的最高级别(之前也是如此,我只是添加了这个):

 signal Sie1_i: std_logic_vector(3 downto 0); 
 signal Sie1_i1: std_logic_vector(3 downto 0);
 signal Sie1_i2: std_logic_vector(3 downto 0);
 signal Sie1_i3: std_logic_vector(3 downto 0);
   .
   .
   .
   when Q18 =>
    Sie1<="0001";
    Sie2<="1000";
    Sie3<="0001";
    Sie4<="1001";    

   end case;    

  end process; 
  Sie1_i <= Sie1;-------- ERROR HERE
  Sie1_i1 <= Sie2; -------- ERROR HERE
  Sie1_i2 <= Sie3; -------- ERROR HERE
  Sie1_i3 <= Sie4; -------- ERROR HERE

   display_1: seg7 port map(Sie1_i, Sie11);
   display_2: seg7 port map(Sie1_i1,Sie21);
   display_3: seg7 port map(Sie1_i2,Sie31);
   display_4: seg7 port map(Sie1_i3,Sie41);

 end behavioral;

1 个答案:

答案 0 :(得分:0)

display_1: seg7 port map(Sie1,Sie11); ------ERROR HERE

Sie1是您实体的输出。您无法从输出中读取。为了解决这个问题,通常你会做类似的事情:

Sie1_i <= Sie1;
display_1: seg7 port map(Sie1_i, Sie11);

并将您之前的代码分配给Sie1_i