进程中端口映射的替代方式?

时间:2016-05-04 22:24:38

标签: vhdl

就我在vhdl中的理解而言,不可能将端口映射到进程内的组件。我很好奇是否有另一种方法可以接近条件情景。

这是我目前正在处理的计算器vhdl代码示例:

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;


-- OP CODE TABLE --
-- 00   :   LOAD --
-- 01   :   ADD/SUB  --
-- 10   :   Print--
-- 11   :   BEQ  --

-- li - RS Values --
-- 00 : R0 --
-- 01 : R1 --
-- 10 : R2 --
-- 11 : R3 --


-- //      add     | op, rs, rd, rt       //
-- //      sub     | op, rs, rd, rt       //
-- //      li      | op, rs, immediate    //
-- //      beq     | op, rs, rd, zero     //
-- //      print   | op, rs, zero, one    //


-- Current Problems --

-- need variables?
-- dont know what to do with numInst

entity Calculator is

port (

    Clock       : in std_logic;
    numInst     : in std_logic_vector (7 downto 0);
    --Max Value of PC? 8 bits
    Instruction : in std_logic_vector (7 downto 0);
    --8 bit instruction
    PC          : out std_logic_vector (7 downto 0);
    --8 bit output, used to retrieve next instruction
    PRINTER     : out std_logic_vector (7 downto 0);
    --8 bit output is set to value of register when instruction display is executed
    ENABLE      : in std_logic;
    --when high, instruction execute, when low, hold-no instruction executed
    RESET       : in std_logic
    --on rising edge, reset register value to 0, restart excution of calculator

);

end Calculator;

architecture Behavorial of Calculator is

component ADD is

port (

    A   : in std_logic_vector(7 downto 0);
    B   : in std_logic_vector(7 downto 0);
    Carry   : out std_logic;
    Sum : out std_logic_vector(7 downto 0)

);
end component;


component decode is

port (

    instr   : in std_logic_vector (7 downto 0);
    op  : in std_logic_vector (1 downto 0);
    rs  : in std_logic_vector (1 downto 0);
    rd  : out std_logic_vector (1 downto 0);
    rt  : out std_logic_vector (1 downto 0)

);
end component;

--need variable or signal to store opcode
--maybe need variable to store values identifier of rs, rt, rd
--random comment for something else...idk
--maybe we dont need a separate register vhdl file, make variable?

signal op, rs, rt, rd: std_logic_vector(1 downto 0):=(others=>'0');
signal immediate, AddOut: std_logic_vector(7 downto 0):=(others=>'0');
signal carrybit: std_logic;
--make register signals? R0, R1, R2, R3 
signal R0, R1, R2, R3: std_logic_vector (7 downto 0) := "00000000";

begin


--portmap
decode port map (Instruction, op, rs, rd, rt);

calc: process (Clock, ENABLE, RESET)

-- use variables opcode, rs, rt, rd  to break up Instruction


begin

    if (ENABLE = '0') then

        --nothing, calculator is disabled

    else --ENABLE at 1



        if (rising_edge(RESET)) then

            PC <= "00000000"; -- restart execution
            op <= "00";
            rs <= "00";
            rt <= "00";
            rd <= "00";

            --registers go to 0

        elsif (rising_edge(Clock)) then

            --          


        elsif (Clock = '1') then
            if (op = "00") then
            --maybe can be used to load values into registers

                if(rd(1)='1') then
                    immediate(7 downto 4):='1';
                    immediate(3 downto 2)<= rd;
                    immediate(1 downto 0)<= rt;
                else
                    immediate(7 downto 4):='0';
                    immediate(3 downto 2)<= rd;
                    immediate(1 downto 0)<= rt;         
                end if;


            --PC = PC + 1
            elsif (op = "01") then --add

                if(rs = "00") then
                    if(rt = "00") then
                        addi00: ADD port map(R0,R0,carrybit,AddOut);
                    elsif(rt = "01") then
                        addi01: ADD port map(R0,R1,carrybit,AddOut);
                    elsif(rt = "10") then
                        addi02: ADD port map(R0,R2,carrybit,AddOut);
                    else
                        addi03: ADD port map(R0,R3,carrybit,AddOut);
                    end if;
                elsif(rs = "01") then
                    if(rt = "00") then
                        addi10: ADD port map(R1,R0,carrybit,AddOut);
                    elsif(rt = "01") then
                        addi11: ADD port map(R1,R1,carrybit,AddOut);
                    elsif(rt = "10") then
                        addi12: ADD port map(R1,R2,carrybit,AddOut);
                    else
                        addi13: ADD port map(R1,R3,carrybit,AddOut);
                    end if;
                elsif(rs = "10") then
                    if(rt = "00") then
                        addi20: ADD port map(R2,R0,carrybit,AddOut);
                    elsif(rt = "01") then
                        addi21: ADD port map(R2,R1,carrybit,AddOut);
                    elsif(rt = "10") then
                        addi22: ADD port map(R2,R2,carrybit,AddOut);
                    else
                        addi23: ADD port map(R2,R3,carrybit,AddOut);
                    end if; 
                else
                    if(rt = "00") then
                        addi30: ADD port map(R3,R0,carrybit,AddOut);
                    elsif(rt = "01") then
                        addi31: ADD port map(R3,R1,carrybit,AddOut);
                    elsif(rt = "10") then
                        addi32: ADD port map(R3,R2,carrybit,AddOut);
                    else
                        addi33: ADD port map(R3,R3,carrybit,AddOut);
                    end if;
                end if;
                --use component of adder vhdl file?
                --PC = PC + 1 ?


                --use adder (subtractor) component
                --PC = PC + 1 ?

            elsif (op = "10") then 

            -- need rs, rt, rd, variable?

                    if (rs = "00") then

                        PRINTER <= R0;
                        --insert print code here
                        --PC = PC + 1 -- to continue to next instruction

                    elsif (rs = "01") then

                        PRINTER <= R1;
                        --insert print code here
                        --PC = PC + 1 -- to continue to next instruction

                    elsif (rs = "10") then

                        PRINTER <= R2;
                        --insert print code here
                        --PC = PC + 1 -- to continue to next instruction
                    else  --(rs = "11") then

                        PRINTER <= R3;
                        --insert print code here
                        --PC = PC + 1 -- to continue to next instruction    

                    end if;


            elsif (op = "11") then --beq

                --if (register1 != register2) then

                        --PC <= PC + 1;

                --else

                        --PC <= PC + 2;

                --end if;

            end if;

        end if;

        elsif (falling_edge(Clock)) then

            if (op = "00") then

                if (rs = "00") then

                    R0 <= immediate;

                elsif (rs = "01") then

                    R1 <= immediate;

                elsif (rs = "10") then

                    R2 <= immediate;

                else --rs = "11"

                    R3 <= immediate;

                end if;

            elsif (op = "01") then

                if (rd = "00") then

                    R0 <= AddOut;--output of adder;

                elsif (rd = "01") then

                    R1 <= AddOut;--output of adder;

                elsif (rd = "10") then

                    R2 <= AddOut;--output of adder;

                else --rd = 11

                    R3 <= Addout;--output of adder;

                end if;

            end if;

        end if;

    end if;

end process calc;

end architecture Behavorial;

我无法真正理解的主要问题是如何在某些情况下使用我的加法器组件(if / else条件)。

1 个答案:

答案 0 :(得分:2)

正如@BrianDrummond所说,你无法让硬件神奇地出现并随意消失。您无法根据硬件的某些输入来确定是否存在硬件块并且不存在。因此,您需要实例化硬件一次,然后控制输入的内容:

signal L, R : std_logic_vector (7 downto 0);

-- snip

addi: ADD port map(L,R,carrybit,AddOut);   -- here is the ADD instance

calc: process (Clock, ENABLE, RESET)

-- snip

        --PC = PC + 1
        elsif (op = "01") then --add

            if(rs = "00") then
                if(rt = "00") then
                    L <= R0; R <= R0;
                elsif(rt = "01") then
                    L <= R0; R <= R1;
                elsif(rt = "10") then
                    L <= R0; R <= R2;
                else
                    L <= R0; R <= R3;
                end if;
            elsif(rs = "01") then
                if(rt = "00") then
                    L <= R0; R <= R0;
                elsif(rt = "01") then
                    L <= R1; R <= R1;
                elsif(rt = "10") then
                    L <= R1 R <= R2;
                else
                    L <= R1; R <= R3;
                end if;
            elsif(rs = "10") then
                if(rt = "00") then
                    L <= R2; R <= R0;
                elsif(rt = "01") then
                    L <= R2; R <= R1;
                elsif(rt = "10") then
                    L <= R2; R <= R2;
                else
                    L <= R3; R <= R3;
                end if; 
            else
                if(rt = "00") then
                    L <= R3; R <= R0;
                elsif(rt = "01") then
                    L <= R3; R <= R1;
                elsif(rt = "10") then
                    L <= R3; R <= R2;
                else
                    L <= R3; R <= R3;
                end if;
            end if;
            --use component of adder vhdl file?

所以,你可以看到我宣布了两个新信号LR,我正在使用你的过程来控制驱动它们的是什么。然后ADD块会添加R0R1R2R3的某种组合。

我已在下面回答了你的问题,但我在你的代码中看到了很多其他问题,即使它有很多问题,我只是快速浏览一下。按顺序出现,不是严肃的顺序:

i)signal R0, R1, R2, R3: std_logic_vector (7 downto 0) := "00000000";

仔细考虑为什么要初始化这些信号。这可能适用于FPGA,但(来自IC设计背景)依赖初始化信号似乎很危险。

ii)您缺少解码器的实例名称(严格来说是标签):

decode port map (Instruction, op, rs, rd, rt);

应该是这样的:

deci : decode port map (Instruction, op, rs, rd, rt);

iii)你真的应该在你的端口地图中使用命名的assoication。而不是:

deci : decode port map (Instruction, op, rs, rd, rt);

做的:

deci : decode port map (instr => Instruction, op => op, rs => rs, rd = rd, rt => rt);

iv)您的流程不适合可合成顺序流程的任何模板:

calc: process (Clock, ENABLE, RESET)
begin    

    if (ENABLE = '0') then    

    else --ENABLE at 1

        if (rising_edge(RESET)) then

        elsif (rising_edge(Clock)) then

        elsif (Clock = '1') then

以下是使用异步重置的顺序进程的模板:

process(clock, async_reset)  -- nothing else should go in the sensitivity list
begin
    -- never put anything here
    if async_reset ='1' then  -- or '0' for an active low reset
        -- set/reset the flip-flops here
        -- ie drive the signals to their initial values
    elsif rising_edge(clock) then  -- or falling_edge(clock)
        -- put the synchronous stuff here
        -- ie the stuff that happens on the rising or falling edge of the clock
    end if;
     -- never put anything here
end process;        

所以,ENABLE不应该在您的敏感列表中;您的流程的第一行应该是:

calc: process (Clock, RESET)

您应该在ENABLE

的测试后测试rising_edge(Clock)信号
        elsif (rising_edge(Clock)) then
           if (ENABLE = '0') then     

您应该测试复位的绝对值,而不是寻找上升沿。而且你不需要所有这些括号。即不是这样:

    if (rising_edge(RESET)) then

这样:

    if RESET = '1' then

这一行是多余的:

elsif (Clock = '1') then

v)你不应该测试时钟的两个边缘。这不是同步设计。您无法在单个进程中测试两个边。这甚至不是可合成的。这需要:

    elsif (falling_edge(Clock)) then

vi)我担心您在此过程中提前R0R3,然后再使用其值。很难确切地看到你的设计意图,但我怀疑这不起作用:

在VHDL中信号在进程挂起之前不会更新。如果您尝试使用先前在过程中分配的信号,您将获得先前分配的值。

常规

我建议你将设计分解为许多较小的流程。对每种硬件都有一个清晰的想法。每个都执行特定功能,例如将输入多路复用到ADD block。例如,考虑:

  • 流程是顺序逻辑还是组合逻辑?

  • 是重置异步还是同步?

  • 有什么输入?

  • 有什么输出?

然后选择合适的模板。我给了一个带有异步复位的顺序进程。这是一个没有异步复位的顺序进程:

process(clock)  -- nothing else should go in the sensitivity list
begin
    -- never put anything here
    if rising_edge(clock) then    -- or falling_edge(clock)
        -- put the synchronous stuff here
        -- ie the stuff that happens on the rising or falling edge of the clock
    end if;
     -- never put anything here
end process;