错误：并发分配或输出端口连接的目标<keys>应为网络类型

Question

这是用于生成AES加密密钥的代码。我已经尝试了所有以前的解决方案，比如@ *和使用时钟，但似乎没有任何效果。请帮帮我。

module key_generator(clk,reset,initial_key,keys,key_gen_done);
input clk;
input reset;
input [7:0] initial_key [3:0][3:0];
output reg [7:0] keys [9:0][3:0][3:0];
output reg key_gen_done;

reg [7:0] constant [9:0];
reg [7:0] constant_temp [9:0];
reg enable;
reg [7:0] addr [3:0];
reg [7:0] data [3:0];
reg [7:0] prev_reg [3:0][3:0];
reg [7:0] temp [3:0];
reg [7:0] gfunc [3:0];
reg [5:0] round;
reg [3:0] state;
reg [3:0] i,j,k;
reg [7:0] output_key [9:0][3:0][3:0];


parameter init1=4'd0,init2=4'd1,init3=4'd2,transfer1=4'd3,transfer2=4'd4,transfer3=4'd5,transfer4=4'd6,update=4'd7,dummy=4'd8, assert_done = 4'd9;


look_up K0(
                .clk(clk),
                .enable(enable),
                .in(addr[0]),
                .out(data[0])
             );

look_up K1(
                .clk(clk),
                .enable(enable),
                .in(addr[1]),
                .out(data[1])
             );

look_up K2(
                .clk(clk),
                .enable(enable),
                .in(addr[2]),
                .out(data[2])
             );

look_up K3(
                .clk(clk),
                .enable(enable),
                .in(addr[3]),
                .out(data[3])
             );
always@(posedge clk) begin
    if(reset) begin
        state <= init1;
        round <= 0;
        enable <= 1;
        key_gen_done <= 0;

        for(i=0;i<4;i=i+1)begin
            for(j=0;j<4;j=j+1)begin
                prev_reg[i][j] <= initial_key[i][j];
            end
        end
    end

    else begin
        case(state)
            init1 : begin
                addr[0] <= prev_reg[1][0];
                addr[1] <= prev_reg[2][0];
                addr[2] <= prev_reg[3][0];
                addr[3] <= prev_reg[0][0];

                if(round==0) begin
                    constant[round] <= 8'd01;
                end

                else begin
                    if(constant[round-1] < 8'd128) begin
                        constant[round] <= constant[round-1]<<1;
                    end
                    else begin
                        constant[round] <= ((constant[round-1])<<1)^8'd27;
                    end
                end


                state <= dummy;
            end

            dummy : begin
                state <= init2;
            end

            init2 : begin
                for(i=0;i<4;i=i+1) begin
                    temp[i] <= data[i];
                end
                state <= init3;
            end
            init3 : begin
                gfunc[0] <= temp[0]^constant[round];
                gfunc[1] <= temp[1];
                gfunc[2] <= temp[2];
                gfunc[3] <= temp[3];
                state <= transfer1;
            end

            transfer1 : begin
                for(i=0;i<4;i=i+1) begin
                    output_key[round][i][0] <= gfunc[i]^prev_reg[i][0];
                end
                state <= transfer2;
            end

            transfer2 : begin
                for(i=0;i<4;i=i+1) begin
                    output_key[round][i][1] <= output_key[round][i][0]^prev_reg[i][1];
                end
                state <= transfer3;
            end

            transfer3 : begin
                for(i=0;i<4;i=i+1) begin
                    output_key[round][i][2] <= output_key[round][i][1]^prev_reg[i][2];
                end
                state <= transfer4;
            end

            transfer4 : begin
                for(i=0;i<4;i=i+1) begin
                    output_key[round][i][3] <= output_key[round][i][2]^prev_reg[i][3];
                end
                state <= update;
            end

            update : begin

                state <= assert_done;
                for(i=0;i<4;i=i+1) begin
                    for(j=0;j<4;j=j+1) begin
                        prev_reg[i][j] <= output_key[round][i][j];
                    end
                end

            end

            assert_done: begin
               round <= round + 1;

               if(round == 10) begin 
                 key_gen_done <= 1;
                  state <= assert_done;
                end
                else
                  state <= init1;

              end
        endcase
    end
end

assign keys = output_key;

endmodule

并且错误如下：

Error:Cannot assign to memory keys directly 
Error:Cannot access memory output_key directly