Question

我对Verilog完全不熟悉，并且对控制台打印的错误有些疑虑。我知道总是阻止不允许电线 - 我不确定分配会做什么，但我知道初始化不会产生我想要的东西。我不确定如何阅读错误或解释它们，我已经在线查看，但似乎找不到与我的具体错误有关的内容。

     module project(input [2:0] p1, input [2:0] p2, input m1, input m2, output reg [6:0] winner);


       // reg mo;  //not allowed 
     // reg mop; //not allowed
always @(*)
begin
if(m1 > 0 )
    case(0)
        0: winner = 16;
        //1: mo = 32; 
        //2: mo = 64;
        //4: mo = 16;
    endcase

if(m2 > 0 )
    case(0)
        0: winner = 1;
        //16: mop = 2;
        //32: mop = 1;
        //64: mop = 4;
    endcase

winner = 0;
case(p1 + p2 + m1 + m2)

        //rock1 & rock2 => tie no one wins
        17: winner = 0; 
        //rock1 & paper2 => player2 won with paper
        33: winner = p2; 
        //rock1 & scissors2 => player1 won with rock
        65: winner = p1; 
        //paper1 & rock2 => player1 won with paper
        18: winner = p1; 
        //paper1 & paper2 => tie no one wins
        34: winner = 0; 
        //paper1 & scissors2 => player2 won with scissors
        66: winner = p2; 
        //scissors1 & rock2 => player2 won with rock 
        20: winner = p2; 
        //scissors1 & paper2 => player1 won with scissors
        36: winner = p1; 
        //scissors1 & scissors2 => tie no one wins
        68: winner = 0;
    endcase
 end
  endmodule

至于我的错误：

WARNING:Par:283 - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:Par:288 - The signal p1<0>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal p1<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal p1<2>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal p2<0>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal m1_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal m2_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal p2<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal p2<2>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:PhysDesignRules:367 - The signal <p1<0>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <p1<1>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <p1<2>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <p2<0>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <m1_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <m2_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <p2<1>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <p2<2>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.

我为多条线道歉，但我认为它只是发生了同样的情况，所以如果我能弄明白我可以做下一行。如果我的问题令人困惑，我很抱歉，感谢您花时间和帮助查看这些混乱的代码。我为凌乱的代码道歉 - 如果人们甚至可以考虑代码。谢谢！

Answer 1

虽然sharvil111所说的是winner永远不会被赋予大于3位宽度的任何东西（注意，只有在你的任务之前，它被注释掉或被赋值winner = 0否定了最后一个案例），这不是这些警告的来源。您面临的问题是：case (p1 + p2 + m1 + m2)。此表达式产生的值为3位宽，因为此表达式中的最长变量为p1，p2为3位宽。因此，该表达式可达到的最大值是3'b7。即使添加到最大位数，也只会产生最大值16（3'b111 {=7} + 3'b111 {=7} + 1'b1 {=1} + 1'b1 {=1} = 5'b10000 {=16};请注意，您需要为Verilog做一些事情，使表达式为5位并且不是3，像添加5'b0应该工作）。 case语句中的值都远高于这两个结果，因此所有这些都被综合工具删除。除了上面提到的winner = 0的分配，无论如何，winner将是7'b0并且没有任何输入重要。因此，您会收到警告。

如果您阅读了警告，则会显示loadless signals;这意味着您的设计中有一些信号不会驱动逻辑，即您的逻辑完全独立于这些信号。因此，综合工具就像优化这些信号以节省空间（你不需要做所有的逻辑来获得从未在任何地方使用过的信号！）。它声称有8个这样的信号，如果你注意到以下警告，继续列出你的所有输入（p1<1>_buf是p1[1]，请注意你有8位的授权，因此8信号，作为输入）。所有警告都与此问题有关。

查看您的代码，我认为您并不意味着添加这些信号。我认为你打算连接它们，制作一个8位长的向量（$size(p1) + $size(p2) + $size(m1) + $size(m2)）。为此，您需要使用连接运算符（{}），如下所示：case ({p1, p2, m1, m2})将通过将每个变量的位置放在彼此旁边来生成大小为8的向量。示例：p1 = 3'b011; p2 = 3'b101; m1 = 1'b1; m2 = 1'b0; {p1, p2, m1, m2} = 8'b011_101_1_0;

Answer 2

似乎警告是由于一些未驱动的输出。您的输出声明为reg [6:0] winner，为7位。它由p1或p2输入端口驱动，分别声明为reg [2:0] p1和reg [2:0] p2，即每个3位。

从第6位到第3位从不在输出端驱动。因此，您的综合工具会发出此警告。

尝试将输出端口声明为reg [2:0] winner。这可能会解决问题。

有关此警告的详细信息，请参阅this和the other one链接。

Verilog编码错误

2 个答案: