Question

我一直有很多编译错误，你可能会在我的另一篇文章中看到。但我能够管理其中的大多数。现在我还有一些，我无法弄清楚为什么他们继续开火。错误主要在2个模块上。一个用作乘数，另一个用作同一模块的测试器。在下面的照片中，您可以看到编译器对我的代码的响应。

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这是代码

这是kkk.v：

module Multiplier_S(output reg [63:0] f_result, input [31:0] a, input [31:0] b);

   wire [31:0] sum[30:0];

   wire [31:0] and_s[31:0];

   wire [63:0] result;


   //bit0
   AND_Bank a_1(and_s[0], a[0], b);

   assign result[0] = and_s[0];

   Shift_Right_32bit shift1(and_s[0], and_s[0], 1);
   assign and_s[0][31:31]=1'b0;
   //bit 1
   AND_Bank a_2(and_s[1], a[1], b);
   FullAdder_32bit adder1(sum[0], result[1], and_s[1], and_s[0]);
   //bit 2
   AND_Bank a_3(and_s[2], a[2], b);
   FullAdder_32bit adder2(sum[1], result[2], and_s[2], sum[0]);
   //bit 3
   AND_Bank a_4(and_s[3], a[3], b);
   FullAdder_32bit adder3(sum[2], result[3], and_s[3], sum[1]);
   //bit 4
   AND_Bank a_5(and_s[4], a[4], b);
   FullAdder_32bit adder4(sum[3], result[4], and_s[4], sum[2]);
   //bit 5
   AND_Bank a_6(and_s[5], a[5], b);
   FullAdder_32bit adder5(sum[4], result[5], and_s[5], sum[3]);
   //bit 6
   AND_Bank a_7(and_s[6], a[6], b);
   FullAdder_32bit adder6(sum[5], result[6], and_s[6], sum[4]);
   //bit 7
   AND_Bank a_8(and_s[7], a[7], b);
   FullAdder_32bit adder7(sum[6], result[7], and_s[7], sum[5]);
   //bit 8
   AND_Bank a_9(and_s[8], a[8], b);
   FullAdder_32bit adder8(sum[7], result[8], and_s[8], sum[6]);
   //bit 9
   AND_Bank a_10(and_s[9], a[9], b);
   FullAdder_32bit adder9(sum[8], result[9], and_s[9], sum[7]);
   //bit 10
   AND_Bank a_11(and_s[10], a[10], b);
   FullAdder_32bit adder10(sum[9], result[10], and_s[10], sum[8]);
   //bit 11
   AND_Bank a_12(and_s[11], a[11], b);
   FullAdder_32bit adder11(sum[10], result[11], and_s[11], sum[9]);
   //bit 12
   AND_Bank a_13(and_s[12], a[12], b);
   FullAdder_32bit adder12(sum[11], result[12], and_s[12], sum[10]);
   //bit 13
   AND_Bank a_14(and_s[13], a[13], b);
   FullAdder_32bit adder13(sum[12], result[13], and_s[13], sum[11]);
   //bit 14
   AND_Bank a_15(and_s[14], a[14], b);
   FullAdder_32bit adder14(sum[13], result[14], and_s[14], sum[12]);
   //bit 15
   AND_Bank a_16(and_s[15], a[15], b);
   FullAdder_32bit adder15(sum[14], result[15], and_s[15], sum[13]);
   //bit 16
   AND_Bank a_17(and_s[16], a[16], b);
   FullAdder_32bit adder16(sum[16], result[16], and_s[16], sum[14]);
   //bit 17
   AND_Bank a_18(and_s[17], a[17], b);
   FullAdder_32bit adder17(sum[16], result[17], and_s[17], sum[15]);
   //bit 18
   AND_Bank a_19(and_s[18], a[18], b);
   FullAdder_32bit adder18(sum[17], result[18], and_s[18], sum[16]);
   //bit 19
   AND_Bank a_20(and_s[19], a[19], b);
   FullAdder_32bit adder19(sum[18], result[19], and_s[19], sum[17]);
   //bit 20
   AND_Bank a_21(and_s[20], a[20], b);
   FullAdder_32bit adder20(sum[19], result[20], and_s[20], sum[18]);
   //bit 21
   AND_Bank a_22(and_s[21], a[21], b);
   FullAdder_32bit adder21(sum[20], result[21], and_s[21], sum[19]);
   //bit 22
   AND_Bank a_23(and_s[22], a[22], b);
   FullAdder_32bit adder22(sum[21], result[22], and_s[22], sum[20]);
   //bit 23
   AND_Bank a_24(and_s[23], a[23], b);
   FullAdder_32bit adder23(sum[22], result[23], and_s[23], sum[21]);
   //bit 24
   AND_Bank a_25(and_s[24], a[24], b);
   FullAdder_32bit adder24(sum[23], result[24], and_s[24], sum[22]);
   //bit 25
   AND_Bank a_26(and_s[25], a[25], b);
   FullAdder_32bit adder25(sum[24], result[25], and_s[25], sum[23]);
   //bit 26
   AND_Bank a_27(and_s[26], a[26], b);
   FullAdder_32bit adder26(sum[25], result[26], and_s[26], sum[24]);
   //bit 27
   AND_Bank a_28(and_s[27], a[27], b);
   FullAdder_32bit adder27(sum[26], result[27], and_s[27], sum[25]);
   //bit 28
   AND_Bank a_29(and_s[28], a[28], b);
   FullAdder_32bit adder28(sum[27], result[28], and_s[28], sum[26]);
   //bit 29
   AND_Bank a_30(and_s[29], a[29], b);
   FullAdder_32bit adder29(sum[28], result[29], and_s[29], sum[27]);
   //bit 30
   AND_Bank a_31(and_s[30], a[30], b);
   FullAdder_32bit adder30(sum[29], result[30], and_s[30], sum[28]);
   //bit 31
   AND_Bank a_32(and_s[31], a[31], b);
   FullAdder_32bit adder31(sum[30], result[31], and_s[31], sum[29]);

   //bit 63 al 32
   initial begin
   result[62:32] = sum[30][30:0];
   end

   if(a[31] || b[31])
      begin
         initial begin
            result[63] = 1'b0;
         end
      end
   else
      begin
         initial begin
            result[63] = 1'b1;
         end
      end
   initial begin
      f_result[63:0] = result[31:0];
   end
endmodule

这是mult_s_test：

module  test_mult;
    reg [31:0] in_A, in_B;
    wire [31:0] result;

    parameter sim_time = 10000;                   //simulation time
    Multiplier_S mult_s (result, in_A, in_B); //syntax for instanciation
    initial #sim_time $finish;                  //simulation time
    initial begin

        #100
       $display("|---------- BEGIN TEST -----------|");
       $display("\t============ negative * positive ==========="); 
        in_A = 32'h00101010;
        in_B = 32'h11111111;
        #100
        $display ("\t Ain       Bin        Output");
        $display ("\t%h   %h    %h\n",in_A,in_B,result);
        #100

        $display("\t============ positive * positive ==========="); 
        in_A = 32'h00101010;
        in_B = 32'h01111111;
        #100
        $display ("\t Ain       Bin        Output");
        $display ("\t%h   %h    %h\n",in_A,in_B,result);
        #100

        $display("\t============ negative * negative ==========="); 
        in_A = 32'h10101010;
        in_B = 32'h11111111;
        #100
        $display ("\t Ain       Bin        Output");
        $display ("\t%h   %h    %h\n",in_A,in_B,result);
        #100

        $display("|---------- END TEST -----------|");
    end
endmodule

请帮帮我，我对verilog真的很新。提前致谢

Verilog：编译错误

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