ACtive-HDL结构模型仿真

时间:2015-09-25 11:41:44

标签: vhdl simulation active-hdl

我已经编写了两个在ISE Design Suit中成功模拟的代码:

-- 2X1 Multiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package mux2to1_pkg is
component mux2to1  
    port(d1,d0: in std_logic;
         s: in std_logic;
         f: out std_logic);
end component;
end mux2to1_pkg;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux2to1 is
port(d1,d0: in std_logic;
     s: in std_logic;
     f: out std_logic);
end mux2to1;          
architecture behavioral of mux2to1 is
begin
f <= (d0 and not s) or
     (d1 and     s);
end behavioral;

-- 6X1 Multiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package mux6to1_pkg is
component mux6to1  
    port(d: in std_logic_vector(5 downto 0);
         s: in std_logic_vector(2 downto 0);
         f: out std_logic);
end component;
end mux6to1_pkg;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.mux2to1_pkg.all;
entity mux6to1 is
port(d: in std_logic_vector(5 downto 0);
     s: in std_logic_vector(2 downto 0);
     f: out std_logic);
end mux6to1;
architecture structural of mux6to1 is
signal m1,m2,m3,m4: std_logic;
begin
mux1: mux2to1 port map(d(5),d(4),s(0),m1);
mux2: mux2to1 port map(d(3),d(2),s(0),m2);
mux3: mux2to1 port map(d(1),d(0),s(0),m3);
mux4: mux2to1 port map(m2,m3,s(1),m4);
mux5: mux2to1 port map(m1,m4,s(2),f);
end structural;

问题是,当我想在Active-HDL中模拟MUX6to1时,输出根本不会改变。这个计划的秘诀是什么? TY。

1 个答案:

答案 0 :(得分:1)

使用此测试台:

$scope.containsComma = function(a) {return a.contains(',')};
$scope.choosePersonBis = function(a) {
    if (a.length == 0) {
        return 'No person';
    } else {
        var split = a.split(',');
        if (split.length > 1) {
            var res = '';
            for (var i = 0; i < split.length; i++) {
                res = res + split[i];
            }
            return res;
        } else {
            return a;
        }
    }
;
$scope.gridPosteOpts = {
    columnDefs : [
        {
            name : 'Title',
            field : 'title',
            enableCellEdit : false
        },
    [...]
    {
        title : 'Person',
        cellTemplate : `
            <div ng-if="grid.appScope.containsComma(row.entity.person)" 
                 class="ui-grid-cell-contents">
              <button type="button" class="btn btn-default"
                      popover="{{grid.appScope.choosePersonBis(row.entity.person)}}"
                      popover-placement="right"
                      popover-trigger="focus">
                Choose person
              </button>
            </div>
            <div ng-if="grid.appScope.notContainsComma(row.entity.person)"
                 class="ui-grid-cell-contents">
              {{grid.appScope.choosePersonBis(row.entity.person)}}
            </div>`
    }
};

它显示的变化如下:

enter image description here

基于此Active-HDL脚本以及mdl.vhd中的上述两个文件:

library ieee;
use ieee.std_logic_1164.all;
entity mdl_tb is
end entity;

library ieee;
use ieee.numeric_std.all;
architecture sim of mdl_tb is
  signal s_d : std_logic_vector(8 downto 0) := (others => '0');
  signal f   : std_logic;
begin
  dut_e : entity work.mux6to1
    port map(d => s_d(5 downto 0),
             s => s_d(8 downto 6),
             f => f);
  process is
  begin
    wait for 1 ns;
    s_d <= std_logic_vector(unsigned(s_d) + 1);
  end process;
end architecture;

顺便说一下。如果您通过以下代码跳过组件声明和相关包,则可以显着减少代码:

# Workspace "prod" create under current and open this workspace
workspace create prod
# Design "prod" create under current workspace
design create -a prod .
# Create to directory under workspace
cd $DSN/..
# Compile
acom ../mdl.vhd
acom ../mdl_tb.vhd
# Load module for simulation
asim work.mdl_tb
# Waveform add
add wave /mdl_tb/*
# Run
run 600 ns 
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